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4.0 Register Set
(Continued)
DP83816
4.2.7 Interrupt Mask Register
This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding
interrupt. During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to
cause an interrupt. ISR bits are always set to 1, however, if the condition is present, regardless of the state of the
corresponding mask bit.
Bit
Bit Name
Description
7
TXDESC
Tx Descriptor
This event is signaled after a transmit descriptor when the INTR bit in the CMDSTS field has been
updated.
6
TXOK
Tx Packet OK
This event is signaled after the last transmit descriptor in a successful transmission attempt has been
updated with valid status.
5
RXORN
Rx Overrun
Set when a receive data FIFO overrun condition occurs.
4
RXIDLE
Rx Idle
This event is signaled when the receive state machine enters the idle state from a running state. This will
happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a descriptor
with OWN set).
3
RXEARLY
Rx Early Threshold
Indicates that the initial Rx Drain Threshold has been met by the incoming packet, and the transfer of the
number of bytes specified by the DRTH field in the RXCFG register has been completed by the receive
DMA engine. This interrupt condition will occur only once per packet.
2
RXERR
Rx Packet Error
This event is signaled after the last receive descriptor in a failed packet reception has been updated with
valid status.
1
RXDESC
Rx Descriptor
This event is signaled after a receive descriptor with the INTR bit set in the CMDSTS field has been
updated.
0
RXOK
Rx OK
Set by the receive state machine following the update of the last receive descriptor in a good packet.
Tag:
IMR
Size:
32 bits
Hard Reset:
00000000h
Offset:
0014h
Access:
Read Write
Soft Reset:
00000000h
Bit
Bit Name
Description
31-26
unused
25
TXRCMP
Transmit Reset Complete
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
24
RXRCMP
Receive Reset Complete
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
23
DPERR
Detected Parity Error
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
22
SSERR
Signaled System Error
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
21
RMABT
Received Master Abort
When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
Summary of Contents for DP83816AVNG
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