J2
Y1
BNC1
BNC2
BNC3
JP1
JP3
National
Semiconductor
G/P ADC, MSOP, Evaluation Board
Rev. 1.1
JP5
BNC1
BNC2
BNC3
CLK INPUT
GND
TPG4
LA1
VR2
VR1
P1
GND
TPG1
GND
TPG2
TP8
+5.5V IN 1
TP6
Input1
Input2
TP7
GND
TPG3
U2, U3, U4
TP1
+V
JP6
INPUT 2
INPUT 1
POWER
L1
L2
TP2 TP5 TP4 TP3
JP2
JP4
VR2
Offset
Adjust
TP6
INPUT 1
Test Point
VR1
VA Supply
Adjust
TP8
+5.5V Input
Test Point
JP6
Clock
Select
BNC3
Ext. Clock
Connection
BNC1
INPUT 1
Connection
BNC2
INPUT 2
Connection
JP2
Input 1 Chan
Select
TP2, TP3,
TP4, TP5
Serial Lines
Test Points
TP7
INPUT 2
Test Point
JP6
Clock
Select
JP1
INPUT 1
AC/DC Couple
JP3
INPUT 2
AC/DC Couple
JP2
Input 1 Chan
Select
Figure 1. Major Components and Test Points of the Evaluation Board
4.0 Functional Description
4.3 ADC Input Bias
The Evaluation Board component locations are shown in
Figure 1
. The board schematic is shown in
Figure 2
.
To maximize ADC performance it is necessary that the
input signal swing cover nearly the entire ADC input
range. If the input biasing is not at the center of the signal
swing, it will not be possible to get maximum signal swing
without clipping of the signal, at which point there will be
excessive distortion.
4.1 Input (signal conditioning) circuitry
The input signal to be digitized should be applied to BNC
connector BNC1 or to BNC2, or to both through (an)
appropriate filter(s). These 50 Ohm inputs are intended to
accept a low-noise sine wave signal of peak-to-peak
amplitude up to the power supply level. To accurately
evaluate the ADC dynamic performance, the input test
signal should be a single frequency passed through a
high-quality band pass filter as described in Section 5.0.
VR2 is provided to allow adjustment of the input bias
point when a.c. input coupling is used. VR2 should be
adjusted to provide a d.c. voltage at TP6 and TP7 that
are one half the DUT supply voltage at TP1.
4.4 ADC clock circuit
The input signal may be either a.c. or d.c. coupled to the
DUT with the setting of jumpers on J1 and JP3. See
schematic
Figure 2
.
The clock signal applied to the ADC can come from
BNC3 or from an on-board oscillator at position Y1 or Y2.
Y1 is for a through-hole TTL oscillator, while Y2 is for a
surface mounted TTL oscillator. Only one oscillator
should be mounted at a time and either an oscillator or
an external generator should be connected. JP6 is used
to select the oscillator source. Shorting pins 1 and 2 of
JP6 selects the on-board oscillator, while shorting pins 2
and 3 selects the oscillator signal at BNC3.
4.2 The ADC reference
The reference voltage for the DUT is the device supply
voltage. Therefore, adjusting this voltage will change the
full scale range of the DUT. Since the operational supply
voltage range of the these ADCs is 2.7V to 5.25V, this is
also the range of the reference voltage.
4
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