Chapter 4
Analog Input
©
National Instruments Corporation
4-19
A single external signal can drive both AI Sample Clock and AI Convert
Clock at the same time. In this mode, each tick of the external clock ca
u
ses
a conversion on the ADC. Fig
u
re 4-14 shows this timing relationship.
Figure 4-14.
Single External Signal Driving AI Sample Clock and
AI Convert Clock Simultaneously
AI Convert Clock Timebase Signal
The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is
divided down to provide one of the possible so
u
rces for AI Convert Clock.
Use one of the following signals as the so
u
rce of AI Convert Clock
Timebase:
•
AI Sample Clock Timebase
•
20 MHz Timebase
AI Convert Clock Timebase is not available as an o
u
tp
u
t on the
I/O connector.
AI Hold Complete Event Signal
The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates a
p
u
lse after each A/D conversion begins. Yo
u
can ro
u
te AI Hold Complete
Event o
u
t to any o
u
tp
u
t PFI terminal.
The polarity of AI Hold Complete Event is software-selectable, b
u
t is
typically config
u
red so that a low-to-high leading edge can clock external
AI m
u
ltiplexers indicating when the inp
u
t signal has been sampled and can
be removed.
AI
Sa
mple Clock
AI Convert Clock
Sa
mple #1
Sa
mple #2
Sa
mple #
3
1 2
3
0
1 2
3
0 1
…
0
Ch
a
nnel Me
asu
red
