Chapter 1 Introduction
SCXI Control Slot
Trigger Bus
Star Triggers
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PCI Arbitration and Clock Signals
SCXI
Connection
Figure 1-3. PXI Star Trigger and Local Bus Routing
Slot 4 of the PXI backplane has connections for a PXI peripheral module
to control the SCXI subsystem. These connections use the available local
bus right pins (PXI_LBRO:12). The SCXI connection passes
communication, timing, and low-voltage analog bus signals between the
SCXI subsystem and the PXI module in slot 4.
The eight PXI trigger lines are bused to each slot. You can use the trigger
lines in a variety of ways. For example, you can use triggers to synchronize
the operation of several different PXI peripheral modules. In other
applications, one module can control carefully timed sequences of
operations performed on other modules in the system. Modules can pass
triggers to one another, allowing precisely timed responses to
asynchronous external events the system is monitoring or controlling.
System Reference Clock
The PXI-1011 supplies the PXI 10 MHz system clock signal
(PXI_CLK10) independently to each peripheral slot. A n independent
buffer (having a source impedance matched to the backplane and a skew
of less than 1 ns between slots) drives the clock signal to each peripheral
slot. You can use this common reference clock signal to synchronize
multiple modules in a measurement or control system. You can drive
PXI_CLK10 from an external source through the PXI_CLK 10_IN pin
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Chassis User Manual
