National Instruments PCIe-6323, User Manual

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7-28
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Chapter 7 Counters
Figure 7-28 shows a generation of a pulse with a pulse delay of four and a pulse width of three
(using the rising edge of Source).
Figure 7-28. Single Pulse Generation with Start Trigger
Pulse Train Generation
Refer to the following sections for more information about the X Series pulse train generation
options:
• Finite Pulse Train Generation
• Retriggerable Pulse or Pulse Train Generation
• Continuous Pulse Train Generation
• Finite Implicit Buffered Pulse Train Generation
• Continuous Buffered Implicit Pulse Train Generation
• Finite Buffered Sample Clocked Pulse Train Generation
• Continuous Buffered Sample Clocked Pulse Train Generation
Finite Pulse Train Generation
Finite pulse train generation creates a train of pulses with programmable frequency and duty
cycle for a predetermined number of pulses, as shown in Figure 7-29. With X Series counters,
the primary counter generates the specified pulse train and the embedded counter counts the
pulses generated by the primary counter. When the embedded counter reaches the specified tick
count, it generates a trigger that stops the primary counter generation.
Figure 7-29. Finite Pulse Train Generation: Four Ticks Initial Delay, Four Pulses
S OURCE
GATE
( S t a rt Trigger)
OUT
En ab le x
S o u rce
Ctr x
Co u nter Armed