Chapter 5
Counters
5-2
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Pause Trigger
You can use pause triggers in edge counting and continuous pulse
generation applications. For edge counting acquisitions, the counter stops
counting edges while the external trigger signal is low and resumes when
the signal goes high or vice versa. For continuous pulse generations, the
counter stops generating pulses while the external trigger signal is low and
resumes when the signal goes high or vice versa.
Counter Timing Signals
Figure 5-2 shows the timing requirements for the gate and source input
signals and the timing specifications for the output signals on your device.
Figure 5-2.
Counter Timing Signals
The gate and out signal transitions shown above are referenced to the rising
edge of the source signal. This timing diagram assumes that the counters
are programmed to count rising edges. The same timing diagram, but with
the source signal inverted and referenced to the falling edge of the source
signal, applies when you program the counter to count falling edges.
The gate input timing parameters are referenced to the signal at the
source input or to one of the internally generated signals on your device.
Figure 5-2 shows the gate signal referenced to the rising edge of a source
signal. The gate must be valid (either high or low) for at least 10 ns before
the rising or falling edge of a source signal so the gate can take effect at that
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SOURCE
GATE
OUT
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time
50 ns minimum
10 ns minimum
10 ns minimum
0 ns minimum
10 ns minimum
80 ns maximum
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