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I-3
PFI synchronization clock
possible sources, 3-15
using front panel PFIs as outputs, 3-15
physical specifications, A-5
PLL
Active LED, 3-7
using the PXI_CLK10 PLL, 3-22
power requirement specifications, A-5
programmable function interface.
See
PFI
PXI backplane clock, 3-11
PXI star trigger bus.
PXI_CLK10
Active LED, 3-7
clock generation, 3-11
DDS phase-lock, 3-9
routing to the CLKOUT connector, 3-8
using front panel PFIs as outputs, 3-15
using the PXI_CLK10 PLL, 3-22
using the PXI/RTSI triggers, 3-17
PXI_CLK10 phase, calibration, 4-1
PXI_CLK10_IN, signal description
PXI_CLK10_OUT, signal description
PXI_STAR <0..12>
asynchronous routing, 3-19, 3-21
signal description (table), 3-10
specifications, A-3
using front panel PFIs as outputs, 3-15
using the PXI star triggers, 3-18
using the PXI/RTSI triggers, 3-17
PXI_TRIG <0..7>
asynchronous routing, 3-19, 3-21
signal description (table), 3-10
specifications, A-4
using front panel PFIs as outputs, 3-15
using the PXI star triggers, 3-18
using the PXI/RTSI triggers, 3-17
PXI_Trig/PXI_Star synchronization clock
possible sources, 3-17
using the PXI/RTSI triggers, 3-17
R
resistors, terminating signals (note), 3-15
routing architecture (figure), 3-13
routing signals
front panel triggers
using as inputs, 3-15
using as outputs, 3-15
generating a single pulse (trigger), 3-22
overview, 3-12
possible sources and destinations
PXI star triggers, 3-18
PXI triggers
asynchronous, 3-18
synchronous, 3-19
RTSI signal names (note), 3-10
S
safety, specifications, A-6
signal descriptions (table), 3-9
signal source, 3-14
possible sources (table), 3-14
single pulse generation, 3-22
software
installing, 2-1
programming choices, overview, 1-2
source
possible sources (table), 3-14
signal, 3-14
specifications
CE compliance, A-7
cleaning, A-6
CLKIN characteristics, A-1
CLKOUT characteristics, A-2
DDS characteristics, A-4
electromagnetic compatibility, A-7
environmental, A-5
environmental management, A-7
OCXO characteristics, A-4