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3-17
Using the PXI/RTSI Triggers
The PXI trigger bus is a set of 8 electrical lines that go to every slot in a segment of a PXI chassis
(multi-drop up to 8 slots). Only one PXI module should drive a particular PXI_Trigger line at a
given time. The signal is then received by modules in all other PXI slots. This feature makes the
PXI triggers convenient in situations where you want, for instance, to trigger several devices,
because all modules will receive the same trigger.
Given the architecture of the PXI trigger bus, triggering signals do not reach each slot at
precisely the same time. A difference of several nanoseconds can occur between slots, especially
in larger PXI chassis (which can have buffers between segments). This delay is not a problem
for many applications. However, if your application requires tighter synchronization, use the
PXI_STAR triggers (refer to next section), or use the PXI trigger bus synchronous to
PXI_CLK10 as shown in Figure 3-11.
The multi-drop nature of the PXI trigger bus can introduce signal integrity issues. Therefore,
National Instruments does not recommend the use of PXI_Trigger lines for clock distribution.
The preferred method for clock distribution is the use of the PXI_STAR triggers. However, the
NI PXI-665
x
Series does support routing of clocks to the PXI_Trigger lines, in case you must
use them.
You can independently select the output signal source for each PXI/RTSI trigger line from one
of the following sources:
•
PFI <0..5>
•
Another PXI/RTSI trigger <0..7> (PXI_TRIG <0..7>)
•
PXI_STAR <0..12>
•
Global software trigger
•
PXI_Trig/PXI_Star synchronization clock
The PXI_Trig/PXI_Star synchronization clock may be any of the following signals:
•
DDS clock
•
PXI_CLK10
•
PFI 0 Input
•
Any of the previously listed signals divided by the first frequency divider (2
n
, up to 512)
•
Any of the previously listed signals divided by the second frequency divider (2
m
, up to 512)
Refer to the
section for more information about the
synchronization clock.
Note
The PXI_Trig/PXI_Star synchronization clock is the same for all routing
operations in which PXI_TRIG <0..7> or PXI_STAR <0..12> is defined as the
output, although the divide-down ratio for this clock (full rate, first divider,
second divider) may be chosen on a per route basis.
