Refer to the
DO Start Trigger Signal
and
DO Pause Trigger Signal
sections in
Digital Output
Timing Signals
for more information about the digital output trigger signals.
Digital Output Timing Signals
The cRIO controller features the following DO timing signals:
•
DO Sample Clock Signal*
•
DO Sample Clock Timebase Signal
•
DO Start Trigger Signal*
•
DO Pause Trigger Signal*
Signals with an * support digital filtering. Refer to the
section for more
information.
DO Sample Clock Signal
The DO Sample Clock signals when all the digital output channels in the task update. DO
Sample Clock can be generated from external or internal sources as shown in the image below.
Figure 43. Digital Output Timing Options
Programmable
Clock
Divider
DO Sample Clock
Timebase
PFI
Analog Comparison Event
Ctr n Internal Output
DO Sample
Clock
Analog Comparison
Event
80 MHz Timebase
20 MHz Timebase
PFI
13.1072 MHz Timebase
12.8 MHz Timebase
10 MHz Timebase
100 kHz Timebase
Routing DO Sample Clock to an Output Terminal
You can route DO Sample Clock to any output PFI terminal. DO Sample Clock is active high
by default.
DO Sample Clock Timebase Signal
The DO Sample Clock Timebase signal is divided down to provide a source for DO Sample
Clock. DO Sample Clock Timebase can be generated from external or internal sources and is
not available as an output from the controller.
NI cRIO-905x User Manual
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© National Instruments
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