Digital Input Timing Signals
The cRIO controller features the following digital input timing signals:
•
DI Sample Clock Signal*
•
DI Sample Clock Timebase Signal
•
DI Start Trigger Signal*
•
DI Reference Trigger Signal*
•
DI Pause Trigger Signal*
Signals with an * support digital filtering. Refer to the
information.
DI Sample Clock Signal
Use the DI Sample Clock signal to sample digital I/O on any slot using parallel digital
modules, and store the result in the DI waveform acquisition FIFO. If the cRIO controller
receives a DI Sample Clock signal when the FIFO is full, it reports an overflow error to the
host software.
A sample consists of one reading from each channel in the DI task. DI Sample Clock signals
the start of a sample of all digital input channels in the task. DI Sample Clock can be generated
from external or internal sources as shown in the following figure.
Figure 40. DI Sample Clock Timing Options
Programmable
Clock
Divider
DI Sample Clock
Timebase
PFI
Analog Comparison Event
Ctr n Internal Output
Sample
Clock
Sigma-Delta Module Internal Output
Analog Comparison
Event
80 MHz Timebase
20 MHz Timebase
PFI
13.1072 MHz Timebase
12.8 MHz Timebase
10 MHz Timebase
100 kHz Timebase
Routing DI Sample Clock to an Output Terminal
You can route DI Sample Clock to any output PFI terminal.
DI Sample Clock Timebase Signal
The DI Sample Clock Timebase signal is divided down to provide a source for DI Sample
Clock. DI Sample Clock Timebase can be generated from external or internal sources. DI
Sample Clock Timebase is not available as an output from the controller.
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NI cRIO-905x User Manual