Figure 35. AI Sample Clock Timing Options
Programmable
Clock
Divider
Sample Clock
Timebase
PFI
Analog Comparison Event
Ctr n Internal Output
AI Sample
Clock
Sigma-Delta Module Internal Output
Analog Comparison
Event
80 MHz Timebase
20 MHz Timebase
PFI
13.1072 MHz Timebase
12.8 MHz Timebase
10 MHz Timebase
100 kHz Timebase
Routing the Sample Clock to an Output Terminal
You can route Sample Clock to any output PFI terminal. Sample Clock is an active high pulse
by default.
AI Sample Clock Timebase Signal
The AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock.
AI Sample Clock Timebase can be generated from external or internal sources. AI Sample
Clock Timebase is not available as an output from the controller.
AI Start Trigger Signal
Use the Start Trigger signal to begin a measurement acquisition which consists of one or more
samples. Once the acquisition begins, configure the acquisition to stop in one of the following
ways:
•
When a certain number of points has been sampled (in finite mode)
•
After a hardware reference trigger (in finite mode)
•
With a software command (in continuous mode)
An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as
a posttriggered acquisition. That is, samples are measured only after the trigger.
When you are using an internal sample clock, you can specify a default delay from the start
trigger to the first sample.
Using a Digital Source
To use the Start Trigger signal with a digital source, specify a source and a rising or falling
edge. Use the following signals as the source:
•
Any PFI terminal
•
Counter n Internal Output
40
|
ni.com
|
NI cRIO-905x User Manual
