Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The FlexRIO adapter module ships with socketed CLIP items that add module I/O to the
LabVIEW project.
NI 5751 CLIP
The NI 5751/5751B ships with the following CLIP items:
1.
NI 5751 CLIP
—The NI 5751 CLIP provides access to 16 analog input channels, eight
digital input lines, and eight digital output lines. This CLIP also contains a SPI interface
to program the ADC registers.
In the NI 5751 CLIP, each Sample Clock cycle generates a sample from the analog input
channels. Three clock sources are available and are selectable using the
Sample Clock
Select
control. The default clock source is the 50 MHz onboard oscillator. Other clock
sources available are DStarA through IOModSyncClock and an external clock through
the front panel SMB connector. This CLIP only supports external Sample Clock rates
from 30 MHz to 50 MHz. Each 14-bit sample is output to LabVIEW as an I16 data type.
The 14-bit data is left-justified and padded with two zeros in the LSBs. The data is
clocked out of the CLIP on the Data Clock signal.
2.
NI 5751 Multidevice Synchronization CLIP
—The NI 5751 Multidevice
Synchronization CLIP provides access to 16 analog input channels, eight digital input
lines, and eight digital output lines. This CLIP also contains a SPI interface to program
the ADC registers. Use this CLIP for applications that require synchronization across
multiple NI 5751 modules.
In the NI 5751 Multidevice Synchronization CLIP, each Sample Clock cycle generates a
sample from the analog input channels. DStarA is the only Sample Clock that is routed.
This CLIP only supports external Sample Clock rates from 30 MHz to 50 MHz. Each 14-
bit sample is output to LabVIEW as an I16 data type. The 14-bit data is left-justified and
padded with two zeros in the LSBs. DStarA is required to be routed to the CLIP from
LabVIEW FPGA. The data is clocked out of the CLIP on the Data Clock signal.
Related Information
NI 5751/5751B Getting Started Guide
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© National Instruments
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