Figure 4.
NI 5751 Hardware Block Diagram
I16
I16
I16
AI A0
AI A7
Analog Connector
ADC
B
ADC
A
Deserializer
I16
AI B8
AI B15
Deserializer
AI 0
AI 7
AI 8
AI 15
DI 0
DI 7
DO 0
Sync Clock
(DStarA)
DO 7
Exter
nal
Cloc
k In
Clock
Multiplexer
50 MHz Internal
Oscillator
Digital
Connector
Sample Clock Select
SPI Write
SPI Device Select
SPI Address
SPI Write Data
Force Initialization
Initialization Done
PLL Unlocked
ADC Error A
ADC Error B
SPI
Engine
NI 5751 Adapter Module
LabVIEW FPGA CLIP
Data Clock
ADC
Control
12
|
ni.com
|
NI 5751/5751B Getting Started Guide
