Figure 6.
NI 5741 Block Diagram
NI 5741
Power Supply
167049A-02: x2
VHDCI
x8
Current
Limit:
10 mA
Offset
2, 4, 6, 8
+25 V
+2.5 V
+9 V
+5 V
–5 V
+3.3 V
Inrush Limiter
Inrush Limiter
Inrush Limiter
Inrush Limiter
+25 V
Reference
V_out
16-bit DAC
1 MSPS
SER_CLK
SER_DATA
REF
7-9
12
10
10
13
11
AO 0:15
PFI
Digital
Interface
SER_CS
Low-Pass
11
NI FLEXRIO
Output Select:
+/– 2.5 or +5
VCCOA
VCCOB
+3.3 V
+12 V
Appendix B: Interfacing with the NI 5741
Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The FlexRIO adapter module ships with socketed CLIP items that add module I/O to the
LabVIEW project.
CLIP and LabVIEW FPGA
The interface between the NI 5741 CLIP and LabVIEW FPGA in the following figures.
If you are using an NI FlexRIO FPGA module with a Virtex-5 FPGA, refer to the following
figure, which shows the relationship between the CLIP and an FPGA VI configured for use
with a Virtex-5 FPGA target.
12
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NI 5741 Getting Started Guide
Summary of Contents for NI 5741
Page 1: ...NI 5741...
