National Instruments DAQ AT-MIO-16X, User Manual

Page: 326 / 330

Index
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National Instruments Corporation I-17 AT-MIO-16X User Manual
description, 4-56
DMA operations, 5-41
servicing update requests, 5-36
DAC Event Strobe Register Group,
4-53 to 4-56
DAC Update Register, 4-55
DAC0 Register
description, 4-44
programming analog output
circuitry, 5-25
DAC1 Register
description, 4-45
programming analog output
circuitry, 5-25
DAQ Clear Register
clearing analog input circuitry, 5-14
description, 4-49
interrupt programming, 5-43
programming DMA operations, 5-41
DAQ Start Register, 4-50
description format, 4-3
Digital Input Register
description, 4-69
digital I/O circuitry, 3-25
programming digital I/O
circuitry, 5-36
Digital I/O Register Group, 4-68 to 4-70
Digital Output Register
description, 4-70
overview, 3-25
programming digital I/O
circuitry, 5-36
DMA Channel Clear Register, 4-58
DMATCA Clear Register
clearing analog output circuitry, 5-32
description, 4-59
interrupt programming, 5-43
programming DMA operations, 5-41
DMATCB Clear Register
clearing analog output circuitry, 5-32
description, 4-60
interrupt programming, 5-43
programming DMA operations, 5-41
External Strobe Register, 4-61
General Event Strobe Register Group,
4-57 to 4-63
programming considerations, 5-1
register map, 4-1 to 4-2
register sizes, 4-3
RTSI Switch Register Group, 4-71 to 4-73
RTSI Switch Shift Register, 4-72
RTSI Switch Strobe Register, 4-73
Single Conversion Register, 4-51
Status Register 1
description, 4-25 to 4-29
servicing update requests, 5-36
Status Register 2, 4-30
TMRREQ Clear Register
clearing analog output circuitry, 5-32
description, 4-54
DMA operations, 5-41
interrupt programming, 5-43
servicing update requests,
5-35 to 5-36
relative accuracy specification
analog input, A-4
analog output, A-7
RETRIG_DIS bit, 4-6
RSE (referenced single-ended input)
description (table), 2-8
recommended configuration (table), 2-22
single-ended connections for floating
signal sources, 2-27
RSI bit, 4-72
RTSI bus clock, CLKMODEB<1..0> bits for
selecting, 4-20 to 4-21
RTSI bus interface circuitry, 3-29 to 3-30
block diagram, 3-29
RTSI bus trigger line, programming,
5-37 to 5-38