National Instruments DAQ AT-MIO-16X User Manual Download Page 322

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Index

National Instruments Corporation

I-13

AT-MIO-16X User Manual

immediate update mode, 3-18
input configurations. See also CONFIGMEM

available input modes, 2-7 to 2-10

DIFF (table), 2-8
NRSE (table), 2-8
RSE (table), 2-8

common-mode signal rejection, 2-29
differential connections

DIFF input configuration, 2-22
floating signal sources, 2-24 to 2-26
ground-referenced signal

sources, 2-23

nonreferenced signal sources,

2-24 to 2-26

recommended configuration (table), 2-22
single-ended connections, 2-26 to 2-27

floating signal sources (RSE

configuration), 2-27

grounded signal sources (NRSE

configuration), 2-28

input multiplexer

address selection bits (CHANSEL

<3..0>), 4-36 to 4-37

description, 3-6

input polarity and range, 2-10 to 2-11

actual range and measurement precision

(table), 2-11

selection considerations, 2-10

installation. See also configuration.

hardware installation, 2-13
unpacking AT-MIO-16X, 1-7

INTCHB<2..0> bits, 4-19
internal update counter, selecting, 5-32
interrupts

controlling with bits in Command

interrupt channel selection, 2-7
interrupt level selection (table), 4-19

PC I/O channel interface, 3-4
programming, 5-43

interval channel scanning

definition, 5-10
programming, 5-12 to 5-14

interval scanning data acquisition timing, 3-14
INTGATE bit, 4-6
I/O connectors

cabling considerations

50-pin I/O connector, 2-43 to 2-44
68-pin I/O connector, 2-44

exceeding maximum ratings

(warning), 2-14

pin assignments

50-pin connector (figure), 2-15, B-2
68-pin connector (figure), 2-16, B-3

signal descriptions (table), 2-17 to 2-19

I/O_INT bit, 4-15

LabVIEW and LabWindows/CVI

software, 1-4

LASTONE bit, 5-16
linear errors

equivalent gain errors in 16-bit systems

(table), A-4

equivalent offset errors in 16-bit systems

(table), A-3

gain error, A-3
postgain offset error, A-3
pregain offset error, A-3

manual. See documentation.
multiple-analog input channel configurations,

programming, 5-15 to 5-16

multiple-channel data acquisition timing,

3-12 to 3-15

continuous scanning, 3-13

Summary of Contents for DAQ AT-MIO-16X

Page 2: ...76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 034...

Page 3: ...CIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or...

Page 4: ...Programming Choices 1 4 National Instruments Application Software 1 4 NI DAQ Driver Software 1 5 Register Level Programming 1 6 Optional Equipment 1 7 Unpacking 1 7 Chapter 2 Configuration and Instal...

Page 5: ...rential Connections for Nonreferenced or Floating Signal Sources 2 24 Single Ended Connection Considerations 2 26 Single Ended Connections for Floating Signal Sources RSE Configuration 2 27 Single End...

Page 6: ...Acquisition Timing 3 13 Interval Scanning Data Acquisition Timing 3 14 Data Acquisition Rates 3 15 Analog Output and Timing Circuitry 3 15 Analog Output Circuitry 3 16 Analog Output Configuration 3 17...

Page 7: ...51 ADC Calibration Register 4 52 DAC Event Strobe Register Group 4 53 TMRREQ Clear Register 4 54 DAC Update Register 4 55 DAC Clear Register 4 56 General Event Strobe Register Group 4 57 DMA Channel...

Page 8: ...ut Channel Configurations 5 15 Programming the Sample Interval Counter 5 16 Programming the Sample Counter s 5 17 Sample Counts 2 through 65 536 5 18 Sample Counts Greater than 65 536 5 18 Programming...

Page 9: ...g Input Calibration 6 9 Analog Output Calibration 6 10 Appendix A Specifications Appendix B I O Connector Appendix C AMD Am9513A Data Sheet Appendix D Customer Communication Glossary Index Figures Fig...

Page 10: ...on Circuitry Block Diagram 3 5 Figure 3 4 ADC Conversion Timing 3 8 Figure 3 5 Single Channel Posttrigger Data Acquisition Timing 3 10 Figure 3 6 Single Channel Pretrigger Data Acquisition Timing 3 11...

Page 11: ...2 3 Available Input Configurations for the AT MIO 16X 2 8 Table 2 4 Actual Range and Measurement Precision Versus Input Range Selection and Gain 2 11 Table 2 5 Recommended Input Configurations for Gr...

Page 12: ...n xiii AT MIO 16X User Manual Table A 1 Equivalent Offset Errors in 16 Bit Systems A 3 Table A 2 Equivalent Gain Errors in 16 Bit Systems A 4 Table A 3 Typical Multiple Channel Scanning Settling Times...

Page 13: ...explains board configuration installation of the AT MIO 16X into the PC signal connections to the AT MIO 16X and cable considerations Chapter 3 Theory of Operation contains a functional overview of t...

Page 14: ...ons Used in This Manual The following conventions are used in this manual Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name fo...

Page 15: ...you plan to program the Am9513A Counter Timer used on the AT MIO 16X Am9513A Am9513 System Timing Controller Customer Communication National Instruments want to receive your comments on our products...

Page 16: ...s Windows Because off the shelf instrumentation amplifiers require 500 sec and more to settle to 16 bit accuracy at high gains when sampling multiple channels National Instruments developed the NI PGI...

Page 17: ...by means of board level calibration DACs You can store calibration DAC constants resulting from the calibration procedure in the onboard EEPROM for later use See Chapter 6 Calibration Procedures for...

Page 18: ...d process control analog function generation 16 bit resolution voltage source and programmable signal attenuation You can use the eight TTL compatible digital I O lines for machine and process control...

Page 19: ...ual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI D...

Page 20: ...buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI self calibration messaging and...

Page 21: ...r level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer using NI DAQ or application softw...

Page 22: ...train gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you Unpacking Y...

Page 23: ...This chapter explains board configuration installation of the AT MIO 16X into the PC signal connections to the AT MIO 16X and cable considerations Figure 2 1 AT MIO 16X with 50 Pin I O Connector Parts...

Page 24: ...ific location of the registers within the register set is determined by the AT MIO 16X decode circuitry AT Bus Interface Operation of the AT MIO 16X multifunction I O board is controlled through acces...

Page 25: ...tory to a base I O address of 220 hex This base address setting is suitable for most systems However if your system has other hardware at this base I O address you must change either the AT MIO 16X ba...

Page 26: ...MIO 16X uses I O address hex 220 through hex 23F in the factory default setting Note If you change the AT MIO 16X base I O address you must make a corresponding change to any software packages you us...

Page 27: ...TIO 10 None Line 5 1A0 hex These settings are software configurable and are disabled at startup time Table 2 2 Switch Settings with Corresponding Base I O Address and Base I O Address Space Switch Se...

Page 28: ...0 0 280 280 29F 1 0 1 0 1 2A0 2A0 2BF 1 0 1 1 0 2C0 2C0 2DF 1 0 1 1 1 2E0 2E0 2FF 1 1 0 0 0 300 300 31F 1 1 0 0 1 320 320 33F 1 1 0 1 0 340 340 35F 1 1 0 1 1 360 360 37F 1 1 1 0 0 380 380 39F 1 1 1 0...

Page 29: ...nels 0 through 3 and Channels 5 through 7 If you use the AT MIO 16X in an AT type computer you should only use DMA Channels 5 through 7 because these are the only 16 bit channels available If you use...

Page 30: ...le 4 9 in Chapter 4 Register Map and Descriptions The results of this configuration are as follows One of Channels 0 through 7 is tied to the positive input of the PGIA One of Channels 8 through 15 is...

Page 31: ...ol up to 16 input channels AI SENSE may be driven by the board analog input ground or left unconnected Considerations for using the RSE configuration are discussed in the Signal Connections section la...

Page 32: ...basis through the configuration memory register Considerations for Selecting Input Ranges Input polarity and range selection depend on the expected input range of the incoming signal A large input ran...

Page 33: ...o the EXTREF pin on the I O connector This signal applied to EXTREF must be between 18 and 18 V Both channels need not be configured for the same mode Table 2 4 Actual Range and Measurement Precision...

Page 34: ...channel range from 0 to 65 535 decimal 0 to FFFF hex Digital I O Configuration The AT MIO 16X contains eight lines of digital I O for general purpose use The eight digital I O lines supplied are conf...

Page 35: ...and hardware The AT MIO 16X does not work if installed in an 8 bit expansion slot PC Series After you have made any necessary changes verified and recorded the switches and jumper settings a form is...

Page 36: ...cludes specifications and connection instructions for the signals given on the AT MIO 16X I O connector Caution Connections that exceed any of the maximum ratings of input or output signals on the AT...

Page 37: ...44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 FOUT GA TE5 OUT2 EXTTMRTRIG GA TE1 EXTCONV EXTTRIG SCANCLK 5V BDIO3 BDIO2 BDIO1...

Page 38: ...49 50 51 52 53 19 20 23 21 22 24 25 26 27 28 29 30 31 32 33 34 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 FOUT OUT5 GATE5 DGND GATE2 EXTTMRTRIG DGND DGND SOURCE5 OUT2 OUT1 GATE1 SOURCE1 EXTCONV DGN...

Page 39: ...ration If desired this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes DAC0 OUT AO GND Analog Channel 0 Output This pin supplies the volta...

Page 40: ...EXTGATE is high A D conversions are enabled EXTCONV DIG GND External Convert A high to low edge on EXTCONV causes an A D conversion to occur Conversions initiated by the EXTCONV signal are inhibited o...

Page 41: ...mode signals connected to ACH 0 15 are routed to the positive input of the AT MIO 16X PGIA In differential mode signals connected to ACH 0 7 are routed to the positive input of the AT MIO 16X PGIA and...

Page 42: ...output voltage is referenced to the AT MIO 16X ground The AT MIO 16X ADC measures this output voltage when it performs A D conversions All signals must be referenced to ground either at the source de...

Page 43: ...rce floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore alr...

Page 44: ...th a differential configuration up to eight analog input channels are available Differential input connections should be used when any of the following conditions are present You are connecting eight...

Page 45: ...s Configuration instructions are included in Chapter 4 Register Map and Descriptions Figure 2 7 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejec...

Page 46: ...Differential Input Connections for Nonreferenced Signals Figure 2 8 shows two bias resistors connected in parallel with the signal leads of a floating signal source If the source is truly floating it...

Page 47: ...but has the disadvantage of loading the source down with the series combination sum of the two resistors If for instance the source impedance is 2 k and the two resistors are each 100 k the resistors...

Page 48: ...not met The AT MIO 16X can be software configured for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal source...

Page 49: ...o Channel 15 is the least sensitive and Channel 0 is the most sensitive Single Ended Connections for Floating Signal Sources RSE Configuration Figure 2 9 shows how to connect a floating signal source...

Page 50: ...he positive and negative inputs of the PGIA and this difference is rejected by the amplifier On the other hand if the input circuitry of the AT MIO 16X is referenced to ground such as in the RSE input...

Page 51: ...on the size of the differential input signal Vdiff V in V in The exact formula for the allowed common mode input range is as follows Vcm max 11 V Vdiff 2 With a differential voltage of 10 V the maximu...

Page 52: ...nd reference point for both analog output channels and for the external reference signal Figure 2 11 shows how to make analog output connections and the external reference input connection to the AT M...

Page 53: ...th respect to DIG GND Digital input specifications referenced to DIG GND VIH input logic high voltage 2 V minimum VIL input logic low voltage 0 8 V maximum IIH input current load logic high input volt...

Page 54: ...d sensing external device states such as the state of the switch in Figure 2 12 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2 1...

Page 55: ...w to high edge whenever an A D conversion begins SCANCLK pulses only when scanning is enabled on the AT MIO 16X SCANCLK is normally low and pulses high for approximately 8 conversion begins The low to...

Page 56: ...driven by the output of Counter 3 of the Am9513A Counter Timer This counter is also referred to as the sample interval counter The output of Counter 3 and the RTSI connection to EXTCONV must be disab...

Page 57: ...counter decrements to zero This mode acquires data both before and after a hardware trigger is received The minimum pulse width allowed is 50 ns The first A D conversion starts within one sample inte...

Page 58: ...ng the EXTTMRTRIG signal from the I O connector This signal updates the DACs when A4RCV is disabled and the appropriate DAC waveform mode is programmed through one of the registers in the AT MIO 16X r...

Page 59: ...Timer is described briefly in Chapter 3 Theory of Operation For detailed programming information consult Appendix C AMD Am9513A Data Sheet For detailed applications information consult the Am9513A Am...

Page 60: ...ed to count an internal timebase then the pulse width is equal to the counter value multiplied by the timebase period For time lapse measurement a counter is programmed to be edge gated An edge is app...

Page 61: ...e gate is applied The frequency of the input signal is then the count value divided by the known gate period Figure 2 18 shows the connections for a frequency measurement application A second counter...

Page 62: ...ating 0 5 V to 7 0 V with respect to DIG GND Am9513A digital input specifications referenced to DIG GND VIH input logic high voltage 2 2 V minimum VIL input logic low voltage 0 8 V maximum Input load...

Page 63: ...clock source by any of the Am9513A counter timers and by the Am9513A frequency division output FOUT The signal applied to a SOURCE input must not exceed a frequency of 6 MHz for proper operation of t...

Page 64: ...for at least 10 nsec after the rising or falling edge of a source signal for the gate to take effect at that source edge The gate high or low period must be at least 145 nsec in duration If an interna...

Page 65: ...he following recommendations apply for all signal connections to the AT MIO 16X Separate AT MIO 16X signal lines from high current or high voltage lines These lines are capable of inducing currents in...

Page 66: ...ns 24 through 50 When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise from switching digital signals coupling into the analog...

Page 67: ...board Figure 3 1 AT MIO 16X Block Diagram I O Connector Mux Mode Selection Switches ADC FIFO PGIA 16 Bit Sampling A D Conversion Analog Muxes V oltage Ref Ground REF 3 Data Acquisition Conversion Con...

Page 68: ...TSI bus interface circuitry The internal data and control buses interconnect the components The theory of operation of each of these components is explained in the remainder of this chapter PC I O Cha...

Page 69: ...to 3FF hex SA5 through SA9 are used to generate the board enable signal SA0 through SA4 are used to select individual onboard registers The address decoding circuitry generates the register select si...

Page 70: ...devices Eight interrupt request lines are available for use by the AT MIO 16X IRQ3 IRQ4 IRQ5 IRQ7 IRQ10 IRQ11 IRQ12 and IRQ15 These interrupt levels are selectable from one of the registers in the AT...

Page 71: ...locking Figure 3 3 shows a block diagram of the analog input and data acquisition circuitry Figure 3 3 Analog Input and Data Acquisition Circuitry Block Diagram EEPROM Calibration Constants ACH0 ACH1...

Page 72: ...in a range of 0 to 65 535 In bipolar mode the ADC returns two s complement values resulting in a range of 32 768 to 32 767 Analog Input Multiplexers The input multiplexer consists of a dual eight to...

Page 73: ...and is beneficial for two reasons Any time an A D conversion is complete the value is saved in the FIFO buffer for later reading and the ADC is free to start a new conversion Secondly the FIFO can co...

Page 74: ...er which the board is used Refer to Chapter 6 Calibration Procedures for additional calibration information Data Acquisition Timing Circuitry This section details the different methods of acquiring A...

Page 75: ...ons work with pretrigger and posttrigger modes with either internal or external timing signals Pretriggering acquires data before a software or hardware trigger is applied Posttriggering acquires data...

Page 76: ...m a 32 bit counter The sample counter decrements its count each time the sample interval counter generates an A D conversion pulse and the sample counter stops the data acquisition process when it cou...

Page 77: ...t is called a pretrigger sequence because the first trigger initiates the sample interval timer without enabling the sample counter Conversions occur after this initial trigger and are stored in the A...

Page 78: ...contained in that memory location are applied to the analog input circuitry For scanning operations a counter steps through successive locations in the configuration memory at a rate determined by th...

Page 79: ...e as the single channel acquisition except for the addition of the channel sequencing and the generation of the SCANCLK signal The first sampled channel is Channel 0 followed in time by Channel 1 and...

Page 80: ...nterval before sequencing through the channel information list again Figure 3 8 shows an example of the interval scanning sequence timing Figure 3 8 Interval Scanning Posttrigger Data Acquisition Timi...

Page 81: ...he new value while the conversion of the last value is still taking place However the circuitry does not always settle to full 16 bit accuracy within the smallest allowed sample period of 10 sec Appen...

Page 82: ...uitry The DAC in each analog output channel generates a voltage proportional to the input voltage reference Vref multiplied by the digital code loaded into the DAC Each DAC can be loaded with a 16 bit...

Page 83: ...bipolar output 1 LSB Vref 32 768 The voltage reference source for each DAC is selectable through one of the AT MIO 16X registers and can be supplied either externally at the EXTREF input or internall...

Page 84: ...the appropriate DAC signal must be wrapped back to the analog input circuitry When the AT MIO 16X leaves the factory locations 96 through 127 of the EEPROM are protected and cannot be modified Locati...

Page 85: ...d RTSI latch are used for posted updating of the DACs Data written to the DACs is buffered by the DAC FIFO to be updated at a later time The DAC FIFO can buffer up to 2 048 values before updating the...

Page 86: ...from Counters 1 2 3 or 5 of the Am9513A Counter Timer it can be supplied from the EXTTMRTRIG signal at the I O connector or it can be obtained by accessing a register in the AT MIO 16X register set I...

Page 87: ...FO buffer to be replenished If waveform cycles of less than 2 048 points are required the data can be transferred to the DAC FIFO only once where it can be cycled through to generate a continuous wave...

Page 88: ...start the generation of the waveform as programmed An example of this added functionality is shown in Figure 3 13 Figure 3 13 FIFO Cyclic Waveform Generation with Disable In this example the entire bu...

Page 89: ...Timer is programmed to count the number of DAC FIFO Retransmit signals When the counter counts the appropriate number of occurrences it terminates the waveform sequence A bit is available in Status R...

Page 90: ...abled or the CYCLICSTOP bit is set Digital I O Circuitry The AT MIO 16X has eight digital I O lines These eight digital I O lines are divided into two ports of four lines each and are located at pins...

Page 91: ...l output value of the port When a port is not enabled reading the Digital Input Register returns the state of the digital I O lines driven by an external device Both the digital input and output regis...

Page 92: ...is 10 MHz which generates a 1 MHz clock input to the Am9513A The Am9513A uses this clock input plus a BRDCLK divided by two input at Source 2 to generate six internal timebases These timebases can be...

Page 93: ...ter GATE input allows counter operation to be gated Once a counter is configured for an operation through software a signal at the GATE input can be used to start and stop counter operation The five g...

Page 94: ...egister is written to An overrun is defined as an error generated when the ADC cannot keep up with its programmed conversion speed The Am9513A SOURCE5 pin is connected to the AT MIO 16X RTSI switch wh...

Page 95: ...nning See the Multiple Channel Data Acquisition section earlier in this chapter The Am9513A 4 bit programmable frequency output channel is located at the I O connector FOUT pin Any of the five interna...

Page 96: ...e any of the seven trigger line signals onto any one or more of the pins A 6 0 This capability provides a completely flexible signal interconnection scheme for any AT Series board sharing the RTSI bus...

Page 97: ...write only or read and write and the size of the register in bits The actual register address is obtained by adding the appropriate register offset to the I O base address of the AT MIO 16X Registers...

Page 98: ...bit 8 bit General Event Strobe Register Group DMA Channel Clear Register DMATCA Clear Register DMATCB Clear Register External Strobe Register Calibration DAC 0 Load Register Calibration DAC 1 Load Re...

Page 99: ...roup is introduced followed by a detailed bit description of each register The individual register description gives the address type word size and bit map of the register followed by a description of...

Page 100: ...roup allow general control and monitoring of the AT MIO 16X hardware Command Registers 1 2 3 and 4 contain bits that control operation of several different pieces of the AT MIO 16X hardware Status Reg...

Page 101: ...sed to store calibration constants When EEPROMCS is set the chip select signal to the EEPROM is enabled Before EEPROMCS is brought high SCLK should first be pulsed high to initialize the EEPROM circui...

Page 102: ...cleared A D conversions take place normally INTGATE can be used as a software gating tool or to inhibit random conversions during setup operations 9 RETRIG_DIS Retrigger Disable This bit controls retr...

Page 103: ...t is disabled 6 SCN2 Scan Mode 2 This bit selects the data acquisition scanning mode used when scanning multiple A D channels If SCN2 is set and SCANEN and DAQEN are set interval channel scanning is u...

Page 104: ...r equal to 65 537 4 RTSITRIG RTSI Trigger This bit controls multiple board synchronization through RTSI Bus triggering If RTSITRIG is set then triggering of the data acquisition sequence by another Na...

Page 105: ...ription 15 A4RCV RTSI A4 Receive This bit controls the signal source for the TMRTRIG Timer Trigger signal The TMRTRIG signal updates the DACs in delayed update mode If A4RCV is set pin A4 of the RTSI...

Page 106: ...SI bus 11 BIPDAC1 Bipolar DAC 1 This bit configures the range of DAC 1 in the analog output section If this bit is set DAC 1 is configured for bipolar operation of Vref to Vref In this mode data writt...

Page 107: ...et the reference used for DAC 0 is the external reference voltage from the I O connector If this bit is cleared the internal 10 Vref is used for the DAC 0 reference 7 EISA_DMA EISA Computer DMA This b...

Page 108: ...imary DMA Channel Selected A DMACHBB2 DMACHBB1 DMACHBB0 Secondary DMA Channel Selected B 0 0 0 DMA Channel 0 0 0 0 DMA Channel 0 0 0 1 DMA Channel 1 0 0 1 DMA Channel 1 0 1 0 DMA Channel 2 0 1 0 DMA C...

Page 109: ...e serial link is enabled Data from channels that have been marked in the channel configuration memory will be transmitted over the RTSI bus If ADCDSP is cleared the serial RTSI link is disabled irresp...

Page 110: ...nal value on the primary DMA channel Channel A or the secondary DMA channel Channel B The interrupt request is serviced by strobing the appropriate DMATC Clear Register When DMATCINT is cleared no DMA...

Page 111: ...terns 8 DMACHA DMA Channel A Enable This bit controls the generation of DMA requests on DMA Channel A as selected in Command Register 2 DMA requests are generated from A D conversions as well as from...

Page 112: ...3 DMA and Interrupt Modes Interface Mode Mode Description IO_INT DMACHA DMACHB ADCREQ DAC1REQ DAC0REQ 0 1 0 0 0 1 Channel A to DAC0 0 1 0 0 1 0 Channel A to DAC1 0 1 0 0 1 1 Channel A to DAC0 and DAC...

Page 113: ...r interrupt 1 0 0 1 1 1 ADC and timer interrupt 1 0 0 0 0 1 Channel A to DAC0 with ADC interrupt 1 1 0 0 1 0 Channel A to DAC1 with ADC interrupt 1 1 0 0 1 1 Channel A to DAC0 and DAC1 interleaved wit...

Page 114: ...nterrupt or DMA request is generated when the DAC is ready to receive data If this bit is cleared no DMA request or interrupt is generated To select a specific mode refer to 1 1 1 0 0 1 Channel A and...

Page 115: ...E is connected to board ground unless the board is configured in the NRSE mode in which case AI SENSE is used as an input If DRVAIS is cleared AI SENSE is used as an input in the NRSE input configurat...

Page 116: ...cleared after a reset condition These bits should be initialized through software Address Base address 06 hex Type Write only World Size 16 bit Bit Map Bit Name Description 15 14 CLKMODEB 1 0 Clock M...

Page 117: ...the analog output section If DAC0DSP is set then the serial link is enabled Data is sent from the AT DSP2200 over the RTSI bus and is accepted by DAC 0 If DAC0DSP is cleared the serial RTSI link is d...

Page 118: ...Analog Output Waveform Modes Waveform Mode Mode Description DACMB3 DACMB2 DACMB1 DACMB0 0 0 0 0 Single update with no timed interrupts 1 0 0 0 Single update with timed interrupts X 0 0 1 DMA access th...

Page 119: ...hen the next end of buffer is encountered If this bit is clear when the DACs are in a cyclic mode the DAC circuitry will restart transmission of the buffer after reaching the final point in the buffer...

Page 120: ...cleared Gate 2 is connected to the internal Gate 2 circuitry on the AT MIO 16X 1 FIFO DAC FIFO or DAC Write Select This bit controls the destination of writes to the analog output DACs DMA transfers...

Page 121: ...urrent acquisition sequence ended on an error condition If DAQCOMP is set and neither OVERFLOW nor OVERRUN is set the data acquisition operation has completed without error When DAQCOMP is set and ADC...

Page 122: ...If ADCFIFOEF is set one or more A D conversion results can be read from the ADC FIFO If the appropriate conversion interrupts are enabled see Table 4 3 and ADCFIFOEF is set the current interrupt indic...

Page 123: ...ether an A D conversion was initiated before the previous A D conversion was complete OVERRUN is an error condition that can occur if the data acquisition sample interval is too small sample rate is t...

Page 124: ...AC FIFO Full Flag This bit reflects the state of the DAC FIFO If DACFIFOFF is clear the DAC FIFO is full and is not ready to receive data If DACFIFOFF is set the DAC FIFO is not full and is able to co...

Page 125: ...s the status of the EEPROM chip select pin Because protection circuitry surrounds the EEPROM having EEPROMCS enabled in Command Register 1 does not necessarily result in the EEPROM being enabled If EE...

Page 126: ...s of the A D converter on the AT MIO 16X during a conversion or calibration process The A D converter on the AT MIO 16X can calibrate its internal circuitry on command by strobing the ADC Calibration...

Page 127: ...FIFO Reading from the ADC FIFO Register location transfers data from the AT MIO 16X ADC FIFO buffer to the PC Writing to the CONFIGMEM Register location sets up channel configuration information for t...

Page 128: ...IFO Register returns meaningless information If the ADCFIFOHF flag is clear in Status Register 1 the ADC FIFO is at least half full with conversion data and 256 FIFO values can be read without checkin...

Page 129: ...the analog input circuitry is configured for the input ranges 10 to 10 V two s complement format is used Two s complement format returns numbers between 32 768 and 32 767 decimal when the ADC FIFO Re...

Page 130: ...ut voltage measured use the following formula V ADC reading 10 V 32 768 Gain Table 4 8 Two s Complement Mode A D Conversion Values Input Voltage Gain 1 A D Conversion Result Range 10 to 10 V Decimal H...

Page 131: ...14 CHAN_AIS Channel Analog Input Sense This bit sets the analog input section for RSE or NRSE mode when CHAN_CAL is cleared When CHAN_CAL is set this bit controls the reference signal connected to th...

Page 132: ...omatically sign extended 11 10 0 Reserved These bits must always be set to zero 9 6 CHANSEL 3 0 Input Channel Select These four bits control the input multiplexer address setting for selecting the ana...

Page 133: ...of the input PGIA for the selected channel The following gains can be selected on the AT MIO 16X 0111 7 7 and 15 1000 8 0 and 8 1001 9 1 and 9 1010 10 2 and 10 1011 11 3 and 11 1100 12 4 and 12 1101...

Page 134: ...value the conversion occurs on the selected channel but the value is not saved in the ADC FIFO In addition if the sample counter is programmed to count samples from Source 4 conversions with the CHAN_...

Page 135: ...memory is primed and does not need to be accessed again until a new channel configuration sequence is desired Conversions either by EXTCONV or by Counter 3 of the Am9513A Counter Timer automatically s...

Page 136: ...CONFIGMEMLD Register with only one value in the list serves only to reload this one value Continual strobing with more than one value in the memory sequences through the channel configuration list In...

Page 137: ...ted on the TMRTRIG signal or the DAC Update Register is strobed In the immediate update mode and the serial mode the DAC FIFOs are not utilized In all other output modes the DAC FIFOs are used The out...

Page 138: ...annel The digital code in the preceding formula is a decimal value ranging from 32 768 to 32 767 Table 4 10 Analog Output Voltage Versus Digital Code Unipolar Mode Digital Code Voltage Output Decimal...

Page 139: ...r Manual Bit descriptions for the registers making up the Analog Output Register Group are given on the following pages 16 384 4000 5 0 V 32 767 7FFF 9 999695 V Table 4 11 Analog Output Voltage Versus...

Page 140: ...r an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 10 hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 0 D 15...

Page 141: ...r an access to the DAC Update Register or a timer trigger is received in one of the prescribed paths Address Base address 12 hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 0 D 15...

Page 142: ...er Group The ADC Event Strobe Register Group consists of six registers that when written to cause the occurrence of certain events on the AT MIO 16X board such as clearing flags and starting A D conve...

Page 143: ...B hex Type Read only Word Size 8 bit Bit map Not applicable no bits used Strobe Effect Clears the channel configuration memory Before the channel configuration memory is written to it must be cleared...

Page 144: ...nfiguration value to the analog input circuitry After the final write to the channel configuration memory accessing the CONFIGMEMLD Register loads the first channel configuration value Writing to the...

Page 145: ...ata acquisition operation in progress empties the ADC FIFO clears the OVERRUN bit in Status Register 1 clears the OVERFLOW bit in Status Register 1 clears the DAQCOMP bit in Status Register 1 clears a...

Page 146: ...Size 8 bit Bit Map Not applicable no bits used Strobe Effect Initiates a programmed data acquisition sequence Note Multiple A D conversion data acquisition operations can be initiated in one of three...

Page 147: ...cable no bits used Strobe Effect Initiates a single ADC conversion Note A D conversions can be initiated in one of two ways by accessing the Single Conversion Register or by applying an active low sig...

Page 148: ...m level calibration Note The ADC_BUSY signal in Status Register 2 should be monitored to determine when the AT MIO 16X ADC calibration cycle is finished The calibration cycle takes approximately 1 25...

Page 149: ...oup The DAC Event Strobe Register Group consists of three registers that when written to cause the occurrence of certain events on the AT MIO 16X board such as clearing flags and updating the analog o...

Page 150: ...us Register 1 and its associated interrupt The analog output DACs can be updated internally and externally in the waveform generation mode through the control of A4RCV If A4RCV is enabled internal upd...

Page 151: ...AC0 and DAC1 simultaneously with the previously written values and removes DAC FIFO data for DAC0 DAC1 or both as programmed Address Base address 18 hex Type Write only Word Size 16 bit Bit Map Not ap...

Page 152: ...er clears parts of the DAC circuitry including emptying the DAC FIFO Address Base address 1E hex Type Read only Word Size 8 bit Bit Map Not applicable no bits used Strobe Effect Empties the DAC FIFO c...

Page 153: ...Group The General Event Strobe Register Group consists of six registers that when written to cause the occurrence of certain events on the AT MIO 16X board such as clearing flags and starting A D con...

Page 154: ...el DMA When the first DMA channel terminal count is reached the circuitry automatically sequences the second DMA channel When the second DMA channel terminal count is reached the circuitry returns to...

Page 155: ...ated from the Channel A terminal counter interrupt When the selected DMA Channel A reaches its terminal count the DMATCA signal in the Status Register is asserted If DMATC interrupts are enabled an in...

Page 156: ...from the Channel B terminal counter interrupt When the selected DMA Channel B terminal count is reached the DMATCB signal in Status Register 1 is asserted If DMATC interrupts are enabled an interrupt...

Page 157: ...connector This signal has a minimum low time of 500 nsec The EXTSTROBE pulse is useful for several applications including generating external general purpose triggers and latching data into external...

Page 158: ...ion DAC 0 Load Register Accessing the Calibration DAC 0 Load Register loads the serial data previously shifted into one of the eight selected 8 bit calibration DACs Address Base address 0A hex Type Wr...

Page 159: ...ion DAC 1 Load Register Accessing the Calibration DAC 1 Load Register loads the serial data shifted into the 12 bit ADC pregain offset calibration DACs Address Base address 1A hex Type Write only Word...

Page 160: ...as general purpose timing for the user The Am9513A registers described here are the Am9513A Data Register the Am9513A Command Register and the Am9513A Status Register The Am9513A contains 18 additiona...

Page 161: ...rs for Counters 1 2 3 4 and 5 Counter Hold Registers for Counters 1 2 3 4 and 5 The Master Mode Register The Compare Registers for Counters 1 and 2 All these registers are 16 bit registers Bit descrip...

Page 162: ...ed through the Am9513A Data Register Address Base address 16 hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 8 1 These bits must always be set when writing to the Am9513A Command...

Page 163: ...ption 15 6 X Don t care bits 5 1 OUT 5 1 Each of these five bits returns the logic state of the associated counter output pin For example if OUT4 is set then the output pin of Counter 4 is at a logic...

Page 164: ...ol the AT MIO 16X digital I O lines The Digital Input Register returns the digital state of the eight digital I O lines A pattern written to the Digital Output Register is driven onto the digital I O...

Page 165: ...digital I O lines Address Base address 1C hex Type Read only Word Size 16 bit Bit Map Bit Name Description 15 8 X Don t care bits 7 4 BDIO 3 0 These four bits represent the logic state of the digital...

Page 166: ...of the digital port Address Base address 1C hex Type Write only Word Size 16 bit Bit Map Bit Name Description 15 8 0 Reserved 7 4 BDIO 3 0 These four bits control the digital lines BDIO 3 0 The bit D...

Page 167: ...several AT MIO 16X signal lines The RTSI switch is programmed by shifting a 56 bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register The routing pattern...

Page 168: ...ch Shift Register is a 1 bit register and must be written to 56 times to shift the 56 bits into the internal register Address Base address 0C hex Type Write only Word Size 8 bit Bit Map Bit Name Descr...

Page 169: ...o in order to load the contents of the RTSI Switch Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSI Switch Strobe Register is written to a...

Page 170: ...In the instructions for setting or clearing bits specific register bits should be set or cleared without changing the current state of the remaining bits in the register However writing to these regi...

Page 171: ...initialized for the AT MIO 16X circuitry to operate properly To initialize the AT MIO 16X hardware complete the following steps 1 Write 0 to Command Registers 1 4 2 Access the following strobe regist...

Page 172: ...e update mode The ADC and DAC FIFOs are cleared The DIO ports A and B are set for input mode Initializing the Am9513A Use the following sequence to initialize the Am9513A Counter Timer All writes are...

Page 173: ...ctr to the Am9513ACommand Register Write 0x0004 to theAm9513A Data Register Write 0xFF08 ctr to the Am9513ACommand Register Write 0x0003 to theAm9513A Data Register Write 0xFF5F to theAm9513A Command...

Page 174: ...hrough a programmed number of channels each having its own gain mode and range setting The channels are scanned in a round robin fashion separated in time by the programmed sample interval The final m...

Page 175: ...ate a single A D conversion through hardware apply an active low pulse to the EXTCONV pin on the AT MIO 16X I O connector See the Timing Connections for Data Acquisition and Analog Output section in C...

Page 176: ...onversion result can be read from the FIFO An ADC FIFO overflow condition occurs if more than 512 conversions are initiated and stored in the ADC FIFO before the ADC FIFO Register is read If this cond...

Page 177: ...trigger condition occurs The data acquisition operation is initiated by writing to the DAQ Start Register or by a falling edge on the EXTTRIG signal Programming multiple A D conversions on a single c...

Page 178: ...e Channel Data Acquisition Programming START Program a single analog input channel gain mode and range Program the sample interval counter Program the sample counter Clear theA D circuitry Enable a si...

Page 179: ...data acquisition There is no delay between the cycles of the scan sequence Continuous channel scanning can be thought of as a round robin approach to scanning multiple channels Interval channel scann...

Page 180: ...ng during multiple A D conversions The SCANEN bit must be set regardless of the type of scanning used continuous or interval otherwise only a single channel is scanned START Program multiple analog in...

Page 181: ...ming steps listed in Figure 5 5 to program scanned multiple A D conversions with a scan interval pseudo simultaneous for posttrigger and pretrigger modes as well as internal and external timing The in...

Page 182: ...isition Programming START Program multiple analog input channels gains modes and ranges END Program the sample interval counter Program the sample counter Clear theA D circuitry Enable an interval sca...

Page 183: ...terval counter has reached its terminal count Be sure that the scan interval counter allows enough time for all conversions in a scan sequence to occur so that conversions are not missed Data Acquisit...

Page 184: ...number of locations in the channel configuration memory are sequenced through by the acquisition circuitry A new channel configuration value is selected after each A D conversion The first conversion...

Page 185: ...ocks are available to the Am9513A 5 MHz 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins Using the EXTCONV...

Page 186: ...A Data Register to store the Counter 3 load value If the sample interval is between 2 and FFFF 65 535 decimal write the sample interval to the Am9513A Data Register If the sample interval is 10000 65...

Page 187: ...5 535 decimal write the sample count to the Am9513A Data Register If the sample count is 10000 65 536 decimal write 0 to the Am9513A Data Register 5 Write FF48 to the Am9513A Command Register to load...

Page 188: ...r to arm Counter 4 8 Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register 9 Write 25 to the Am9513A Data Register to store the Counter 5 mode value 10 Write FF0D to the Am9...

Page 189: ...y of the Am9513A SOURCE input pins To program the scan interval counter use the following programming sequence All writes are 16 bit operations All values given are hexadecimal 1 Write FF02 to the Am9...

Page 190: ...been configured and programmed the acquisition sequence is initiated when a trigger is received A trigger can be initiated through software or hardware To initiate the data acquisition operation thro...

Page 191: ...1 16 bit read 2 If the OVERRUN or OVERFLOW bits are set the data acquisition sequence has been halted because one of these error conditions has occurred Clear the A D circuitry by writing to DAQ Clear...

Page 192: ...To reset a particular counter in the Am9513A use the following programming sequence All writes are 16 bit operations All values given are hexadecimal The equation 2 ctr 1 means 2 raised to ctr 1 If c...

Page 193: ...nter X mode register Store the Counter X mode value Store a nonterminal count value Load Counter X Write 0xFFC0 2 ctr 1 to theAm9513A Command Register Write 0x0003 to the Am9513A Data Register Write 0...

Page 194: ...FIFO is used to buffer the incoming data to both of the DAC channels Because this FIFO is 2 048 values deep the last value buffered by the DAC FIFO could lag the output of the DAC channel by up to 2...

Page 195: ...case of this mode occurs when the buffer fits entirely within the DAC FIFO where it is cycled through If this is true and the CYCLICSTOP bit in Command Register 4 is set DAC updating stops at the nex...

Page 196: ...the analog output circuitry including the DAC FIFO Program the update interval counter Set theA4RCV bit in Command Register 2 Set the waveform generation mode Service update requests Clear theA4RCV b...

Page 197: ...ached This removes a large burden on the PC bus for continually updating data in the DAC FIFO Also due to the smaller buffer size the hardware has more control over the updating and cycling through of...

Page 198: ...Clear the analog output circuitry including the DAC FIFO Program the update interval counter Set theA4RCV bit in Command Register 2 Set the waveform generation mode Service update requests Clear theA4...

Page 199: ...ount buffer cycles in this mode If Counter 5 is being used for the update signal then only Counters 1 and 2 are available for cycle counting Once the cycle counter reaches the end of its count DAC upd...

Page 200: ...time between cycles the cycle interval then restarts the sequence This END START Clear the analog output circuitry including the DAC FIFO Program the update interval counter Set theA4RCV bit in Comman...

Page 201: ...ernal Update Counter Select the desired signal at the RTSI switch to be used for updating the DACs OUT1 OUT2 OUT3 available as EXTCONV and OUT5 are available for updating To route these update signals...

Page 202: ...25 Selects 100 Hz clock 0525 Selects signal at SOURCE5 input as clock counts the rising edge of the signal 6 MHz maximum 3 Write FF08 n to the Am9513A Command Register to select the Counter n Load Reg...

Page 203: ...sired cycle count to the Am9513A Data Register to store the Counter n load value 5 Write the following value to the Am9513A Command Register to load Counter n FF41 Load Counter 1 FF42 Load Counter 2 F...

Page 204: ...ter you complete this programming sequence Counter 2 is configured to count the desired interval after each rising edge on GATE2 is encountered The terminal count active low edge will restart the wave...

Page 205: ...Command Register 2 See the register bit descriptions earlier in this chapter for more information To enable digital output port A set the DIOPAEN bit in Command Register 2 To enable digital output po...

Page 206: ...ration and Installation The Timing I O Circuitry section in Chapter 3 Theory of Operation explains how the Am9513A is used on the AT MIO 16X board Initialization of the Am9513A as required by the AT M...

Page 207: ...bits A4DRV A4RCV A2DRV and A2RCV in Command Register 2 To drive the RTSI switch pin A2 with the signal OUT2 set the A2DRV bit in Command Register 2 Otherwise clear the A2DRV bit To drive the signal G...

Page 208: ...7 crossbar switch which can be programmed to connect any of the signals on the A side to any of the signals on the B side and vice versa To do this a 56 bit pattern is shifted into the RTSI switch by...

Page 209: ...TEN is the output enable bit for that pin If the OUTEN bit is set the pin is driven by the selected source signal the pin acts as an output pin If the OUTEN bit is cleared the pin is not driven regard...

Page 210: ...pattern right once and repeating this two step operation a total of 56 times Only bit 0 of the word written to the RTSI Switch Shift Register is used The higher order bits are ignored Programming DMA...

Page 211: ...r writes to the DACs depending on which channel requested a DMA transfer If single channel interleaved DMA is selected for writing data to the DACs then one buffer services both DAC 0 and DAC 1 This i...

Page 212: ...rce of the interrupt through reading Status Register 1 If ADC FIFOEF or ADC FIFOHF is true a conversion interrupt has occurred Reading from the ADC FIFO Register clears these interrupt conditions Writ...

Page 213: ...put sections and writing values to the appropriate calibration DACs to null out the errors There are five calibration DACs associated with the analog input section and four calibration DACs with the a...

Page 214: ...bruary 125 Day of reference calibration for example 29 29th Factory Information Factory BipolarArea Factory UnipolarArea LoadArea UserArea 7 UserArea 6 UserArea 5 UserArea 4 UserArea 3 UserArea 2 User...

Page 215: ...lar Pregain Offset LSB 114 Factory DAC Channel 1 Bipolar Offset 113 Factory DAC Channel 0 Bipolar Offset 112 Factory DAC Channel 1 Bipolar Gain 111 Factory DAC Channel 0 Bipolar Gain 110 Factory ADC B...

Page 216: ...s of locations 96 through 127 While at the factory these locations can be accessed for a read or a write operation but in the field these locations can only be read from These locations cannot and sho...

Page 217: ...on the revision or subrevision of the board Figure 6 3 Configuration Memory Depth Field If the Configuration Memory Depth Field contains the binary value XXXX0001 where X indicates don t care bits th...

Page 218: ...f the DAC FIFO is 2 048 values deep and a half full interrupt is generated then 1 024 values can be read This can have a significant performance impact on software speed Figure 6 5 Area Information Fi...

Page 219: ...e of 25 C After the value of the reference is determined the value should be stored in the EEPROM so that it can be used by the input and output calibration routines The calibration procedure which de...

Page 220: ...d The value of this voltage reference is determined through the reference calibration routine which requires a known external voltage between 5 and 9 99 V to be connected differentially on any desired...

Page 221: ...iplied by the gain of the PGIA To calibrate this offset the routine grounds the inputs of the PGIA measures the input at two different gains and adjusts CALDAC8 until the measured offset in LSBs is in...

Page 222: ...3 Connect AO GND to the negative sides of the channels selected in steps 1 and 2 Do not tie AO GND to AI GND as this will complete a ground loop potentially introducing offset calibration errors of se...

Page 223: ...analog output and AO GND The gain error is always calibrated immediately after the offset is calibrated Notice that CALDAC4 and CALDAC5 adjust the gain by varying the values of the internal DAC refer...

Page 224: ...Maximum sampling rate 100 ksamples sec Relative accuracy 1 5 LSB maximum over temperature 0 75 LSB typical Differential nonlinearity DNL 1 LSB maximum no missing codes over temperature 0 5 LSB typical...

Page 225: ...erence After calibration 0 00366 36 6 ppm maximum Before calibration any gain 0 215 2 150 ppm maximum Gain 1 0 02 200 ppm maximum with gain error adjusted to 0 at gain 1 Temperature coefficient any ga...

Page 226: ...set error plus the gain times the pregain offset error Gain error is the amount of possible deviation from ideal gain expressed as a proportion of the gain The total linear measurement error for a giv...

Page 227: ...og values that can be input to produce that code ideally 1 LSB A specification of 1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs that is no missing codes and that no code w...

Page 228: ...el 1 When the multiplexer switches to Channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in bipolar mode The approximately 4 V step from 4 V to 1 mV is 2...

Page 229: ...r interrupts Maximum update rate 100 ksamples sec Relative accuracy nonlinearity 4 LSB maximum 2 LSB typical bipolar 8 LSB maximum 4 LSB typical bipolar Differential nonlinearity 0 5 LSB maximum monot...

Page 230: ...he amount of possible voltage offset error in the analog output circuitry expressed in mV Gain error is the amount of possible deviation from ideal gain of the analog output circuitry expressed as a p...

Page 231: ...5 LSB Digital I O Compatibility TTL compatible Output current source capability Can source 2 6 mA at VOH at 2 4 V min Output current sink capability Can sink 24 mA at VOL at 0 5 V max Timing I O Numb...

Page 232: ...ion 2 0 A typical at 5 VDC Power available at I O connector 4 75 V to 5 25 V at 1 A Physical Board dimensions 13 3 by 4 5 in I O connector 50 pin male ribbon cable connector or 68 pin male shielded ca...

Page 233: ...ion B 1 AT MIO 16X User Manual Appendix B I O Connector This appendix describes the pinout and signal names for the AT MIO 16X 50 pin I O connector and the 68 pin I O connector Figure B 1 shows the AT...

Page 234: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 FOUT GA TE5 OUT2 EXTTMRTRIG GA TE1 EXTCONV EXTTRIG SCANCLK 5V BDIO3 BDIO2 BDIO1 BDIO0 DIG GND EXTREF DAC0 OUT ACH15 ACH14 ACH1...

Page 235: ...1 52 53 19 20 23 21 22 24 25 26 27 28 29 30 31 32 33 34 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 FOUT OUT5 GATE5 DGND GATE2 EXTTMRTRIG DGND DGND SOURCE5 OUT2 OUT1 GATE1 SOURCE1 EXTCONV DGND DGND D...

Page 236: ...node when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes 22 20 DAC0 OUT Analog Channe...

Page 237: ...ge on EXTTRIG initiates the sequence In pretrigger applications the first high to low edge of EXTTRIG initiates pretrigger conversions while the second high to low edge initiates the posttrigger seque...

Page 238: ...IG will also generate a timed interrupt if enabled 5 45 GATE2 GATE2 This pin is from the Am9513A Counter 2 signal 38 46 OUT2 OUTPUT2 This pin is from the Am9513A Counter 2 signal 37 47 SOURCE5 SOURCE5...

Page 239: ...Am9513A System Timing Controller integrated circuit Advanced Micro Devices Inc data sheet This controller is used on the AT MIO 16X 1 Copyright Advanced Micro Devices Inc 1989 Reprinted with permissi...

Page 240: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 2 National Instruments Corporation...

Page 241: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 3 AT MIO 16X User Manual...

Page 242: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 4 National Instruments Corporation...

Page 243: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 5 AT MIO 16X User Manual...

Page 244: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 6 National Instruments Corporation...

Page 245: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 7 AT MIO 16X User Manual...

Page 246: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 8 National Instruments Corporation...

Page 247: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 9 AT MIO 16X User Manual...

Page 248: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 10 National Instruments Corporation...

Page 249: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 11 AT MIO 16X User Manual...

Page 250: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 12 National Instruments Corporation...

Page 251: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 13 AT MIO 16X User Manual...

Page 252: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 14 National Instruments Corporation...

Page 253: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 15 AT MIO 16X User Manual...

Page 254: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 16 National Instruments Corporation...

Page 255: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 17 AT MIO 16X User Manual...

Page 256: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 18 National Instruments Corporation...

Page 257: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 19 AT MIO 16X User Manual...

Page 258: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 20 National Instruments Corporation...

Page 259: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 21 AT MIO 16X User Manual...

Page 260: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 22 National Instruments Corporation...

Page 261: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 23 AT MIO 16X User Manual...

Page 262: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 24 National Instruments Corporation...

Page 263: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 25 AT MIO 16X User Manual...

Page 264: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 26 National Instruments Corporation...

Page 265: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 27 AT MIO 16X User Manual...

Page 266: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 28 National Instruments Corporation...

Page 267: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 29 AT MIO 16X User Manual...

Page 268: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 30 National Instruments Corporation...

Page 269: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 31 AT MIO 16X User Manual...

Page 270: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 32 National Instruments Corporation...

Page 271: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 33 AT MIO 16X User Manual...

Page 272: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 34 National Instruments Corporation...

Page 273: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 35 AT MIO 16X User Manual...

Page 274: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 36 National Instruments Corporation...

Page 275: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 37 AT MIO 16X User Manual...

Page 276: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 38 National Instruments Corporation...

Page 277: ...Appendix C AMD Am9513A Data Sheet National Instruments Corporation C 39 AT MIO 16X User Manual...

Page 278: ...Appendix C AMD Am9513A Data Sheet AT MIO 16X User Manual C 40 National Instruments Corporation...

Page 279: ...ms does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services National Instruments has BBS...

Page 280: ...d your software to obtain support Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086...

Page 281: ...______________________________________________ _______________________________________________________________________________ National Instruments hardware product model __________ Revision _________...

Page 282: ..._____ Base I O address of other boards _____________________________________________________ DMA channels of other boards ______________________________________________________ Interrupt level of othe...

Page 283: ...__________________________________________________ _______________________________________________________________________________ _____________________________________________________________________...

Page 284: ...16X User Manual Glossary Numbers Symbols percent positive of or plus negative of or minus per degree ohm A A amperes AC alternating current Prefix Meanings Value p pico 10 12 n nano 10 9 micro 10 6 m...

Page 285: ...nctions such as addition subtraction multiplication division inversion AND OR NAND and NOR AMD Advanced Micro Devices amplification a type of signal conditioning that improves accuracy in the resultin...

Page 286: ...uter BIOS functions embody the basic operations needed for successful use of the computer s hardware resources bipolar a signal range that includes both positive and negative values for example 5 V to...

Page 287: ...ls to form ports Ports usually consist of either four or eight digital channels channel clock the clock controlling the time interval between individual channel sampling within a scan Boards with simu...

Page 288: ...digital to analog converters DACs for analog output digital input or output ports and counter timers are conversion devices conversion time the time required in an analog input or output system from...

Page 289: ...f both AC and DC signals DCS distributed control system a large scale process control system characterized by a distributed network of processors and I O subsystems that encompass control user interfa...

Page 290: ...er ground whose difference is measured differential a way you can configure your device to read signals in which you do measurement system not need to connect either input to a fixed reference such as...

Page 291: ...ROM electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed EGA enhanced graphics adapter EISA extended industry standard architecture ele...

Page 292: ...vices to temporarily store incoming or outgoing data until that data can be retrieved or output For example an analog input FIFO stores the results of A D conversions until the data can be retrieved i...

Page 293: ...pin a counter input pin that controls when counting occurs in your application glitch GPIB General Purpose Interface bus synonymous with HP IB The standard bus used for controlling electronic instrum...

Page 294: ...cables and so on hardware triggering a form of triggering where you set the start time of an acquisition and gather data at a known position in time relative to a trigger signal HCT high speed CMOS T...

Page 295: ...circuitry input bias current the current that flows into the inputs of a circuit input impedance the measured resistance and capacitance between the input terminals of a circuit input offset current...

Page 296: ...he computer for safety purposes This protects you and your computer from large voltage spikes and makes sure the measurements from the DAQ device are not affected by differences in ground potentials i...

Page 297: ...dules that are relevant to your application are linked in while those object modules that are not relevant are not linked linearity the adherence of device response to the equation R KS where R respon...

Page 298: ...The MITE supports bus mastering for high speed data transfers over the PCI bus MS million samples MSB most significant bit MTBF mean time between failure multiplexed mode an SCXI operating mode in whi...

Page 299: ...oltage signals that are not connected to an absolute sources reference or system ground Also called floating signal sources Some common example of nonreferenced signal sources are batteries transforme...

Page 300: ...rate the maximum rate of change of analog output voltage from one level to another P parallel mode a type of SCXI operating mode in which the module sends each of its input channels directly to a sepa...

Page 301: ...lements can be processed simultaneously from different instructions PLC programmable logic controller a highly reliable special purpose computer used in industrial monitoring and control applications...

Page 302: ...nd control codes used to transfer data between computers and peripherals through a communications channel such as the GPIB bus proximity sensor a device that detects the presence of an object without...

Page 303: ...t of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 percent of full scale resource locking a technique whereby a device is signaled not to use its local...

Page 304: ...or more analog or digital input samples Typically the number of input samples in a scan is equal to the number of channels in the input group For example one pulse from the scan clock produces one sc...

Page 305: ...m for digitizing signal divider performing frequency division on an external signal SIMM single in line memory module SMB a type of miniature coaxial signal connector SNR signal to noise ratio the rat...

Page 306: ...equire dip switches or jumpers to configure resources on the devices also called Plug and Play devices synchronous 1 hardware a property of an event that is synchronized to a reference clock 2 softwar...

Page 307: ...e circuitry of a signal conditioning system into measuring physical phenomena transfer rate the rate measured in bytes s at which data is moved from source to destination after software initialization...

Page 308: ...igh VIL volts input low Vin volts in VISA a new driver software architecture developed by National Instruments to unify instrumentation softwareGPIB DAQ and VXI It has been accepted as a standard for...

Page 309: ...voltage that should be applied to a product in normal use normally well under the breakdown voltage for safety margin See also Breakdown Voltage Z zero overhead looping the ability of a high performa...

Page 310: ...bit 4 30 ADC Calibration Register 4 52 ADC conversion timing 3 8 ADC Event Strobe Register Group 4 46 to 4 52 ADC Calibration Register 4 52 CONFIGMEMCLR Register description 4 47 programming multiple...

Page 311: ...67 Am9513A Command Register 4 66 Am9513A Data Register 4 65 Am9513A Status Register 4 67 programming general considerations 5 37 resource allocation considerations 5 1 to 5 2 sample counters 5 17 to 5...

Page 312: ...t channel configurations 5 15 register map 4 1 analog input specifications linear errors A 3 to A 4 equivalent gain errors in 16 bit systems table A 4 equivalent offset errors in 16 bit systems table...

Page 313: ...roducts table 2 4 to 2 5 example switch settings figure 2 3 switch settings with base I O address and address space table 2 5 to 2 6 BDIO 0 3 signal description table 2 17 B 4 digital I O circuitry 3...

Page 314: ...A 4 29 EISA_DMA 4 11 EXTREFDAC0 4 11 EXTREFDAC1 4 11 EXTTRIG_DIS 4 24 FIFO DAC 4 24 GATE2SEL 4 24 5 32 INTCHB 2 0 4 19 INTGATE 4 6 I O_INT 4 15 OUT 5 1 4 67 OUTEN 5 40 OVERFLOW 4 27 5 7 5 22 OVERRUN 4...

Page 315: ...ital I O circuitry 5 36 Command Register 3 4 13 to 4 19 Command Register 4 4 20 to 4 24 common mode signal rejection 2 29 ComponentWorks software 1 4 concatenating counters 2 39 CONFIGCLK signal 3 29...

Page 316: ...cy measurements 2 39 input and output ratings 2 40 overview 2 37 pulse width measurements 2 38 time lapse measurements 2 38 timing requirements figure 2 41 timing specifications 2 40 to 2 43 counter t...

Page 317: ...to 3 20 waveform circuitry figure 3 19 waveform timing circuitry 3 20 to 3 22 DAC0 Register description 4 44 programming analog output circuitry 5 25 DAC0DSP bit 4 21 DAC0OUT signal analog output conn...

Page 318: ...r s 5 17 to 5 20 sample interval counter 5 16 to 5 17 scan interval counter 5 20 to 5 21 servicing data acquisition operations 5 22 single conversions flow chart 5 6 generating single conversions 5 6...

Page 319: ...digital I O circuitry 5 36 register map 4 2 Digital Output Register See Digital I O Register Group DIOPAEN bit description 4 14 programming digital I O circuitry 5 36 DIOPBEN bit description 4 13 pro...

Page 320: ...trobe Register Group General Event Strobe Register Group event counting application 2 37 to 2 38 EXTCONV signal description table 2 18 B 5 generating single conversions 5 5 to 5 6 programming sample c...

Page 321: ...o 2 42 RTSI bus interface circuitry 3 30 timing I O circuitry 3 27 to 3 29 GATE1 signal description table 2 18 B 5 RTSI switch connections table 5 38 GATE2 signal table 2 18 B 6 GATE2SEL bit descripti...

Page 322: ...O 16X 1 7 INTCHB 2 0 bits 4 19 internal update counter selecting 5 32 interrupts controlling with bits in Command Register 3 4 13 to 4 19 interrupt channel selection 2 7 interrupt level selection tabl...

Page 323: ...terface circuitry 3 30 timing I O circuitry 3 27 to 3 29 OUT 5 1 bits 4 67 OUT1 signal description table 2 18 B 6 selecting internal update counter 5 32 OUT2 signal description table 2 18 B 6 RTSI swi...

Page 324: ...urations 5 15 to 5 16 programmed cycle waveform generation 5 28 to 5 30 pulsed cyclic waveform generation 5 30 to 5 32 resetting hardware 5 22 to 5 24 sample counter s 5 17 to 5 20 sample interval cou...

Page 325: ...Data Register 4 65 Am9513A Status Register 4 67 Analog Input Register Group 4 31 to 4 40 Analog Output Register Group 4 41 to 4 43 analog output voltage versus digital code bipolar mode table 4 42 to...

Page 326: ...operations 5 41 DMATCB Clear Register clearing analog output circuitry 5 32 description 4 60 interrupt programming 5 43 programming DMA operations 5 41 External Strobe Register 4 61 General Event Stro...

Page 327: ...SCANCLK signal description table 2 18 B 5 multiple channel data acquisition 3 12 3 13 timing connections 2 33 timing I O circuitry 3 29 SCANDIV bit description 4 6 programming multiple analog input c...

Page 328: ...nel programming 5 15 single channel data acquisition timing 3 9 to 3 12 See also data acquisition programming posttrigger data acquisition timing 3 10 to 3 11 pretrigger data acquisition timing 3 11 t...

Page 329: ...3 23 FIFO pulsed waveform generation 3 23 to 3 24 waveform circuitry 3 18 to 3 20 waveform timing circuitry 3 20 to 3 22 data acquisition timing circuitry 3 8 to 3 12 block diagram 3 5 data acquisitio...

Page 330: ...es table 4 34 U unipolar input 2 10 unipolar mode analog output voltage versus digital code table 4 42 unipolar output 2 12 unpacking AT MIO 16X 1 7 update counter selecting 5 32 update interval count...

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