National Instruments DAQ AT-MIO-16X, User Manual, Page: 204 / 330

Chapter 5 Programming
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National Instruments Corporation 5-35 AT-MIO-16X User Manual
2. Write the mode value to the Am9513A Data Register to store the
Counter 2 mode value. Am9513A counter mode information can be
found in Appendix C, AMD Am9513A Data Sheet.
C225 — Selects 5-MHz clock (from SOURCE2 pin)
CB25 — Selects 1-MHz clock
CC25 — Selects 100-kHz clock
CD25 — Selects 10-kHz clock
CE25 — Selects 1-kHz clock
CF25 — Selects 100-Hz clock
C525 — Selects signal at SOURCE5 input as clock
(counts the rising edge of the signal, 6 MHz maximum)
3. Write FF0A to the Am9513A Command Register to select the
Counter 2 Load Register.
4. Write the desired cycle interval plus one to the Am9513A Data
Register to store the Counter 2 load value.
5. Write FF42 to the Am9513A Command Register to load Counter 2.
6. Write FFF2 to the Am9513A Command Register to decrement
Counter 2.
7. Write FF22 to the Am9513A Command Register to arm Counter 2.
After you complete this programming sequence, Counter 2 is
configured to count the desired interval after each rising edge on
GATE2 is encountered. The terminal count active low edge will restart
the waveform generation process.
Servicing Update Requests
Updating the DACs using a timer signal can be handled using either
polled I/O, interrupts or DMA requests. Upon the application of a
falling edge signal to the TMRTRIG* signal, both DACs are updated
and TMRREQ in Status Register 1 is set and if DMA or interrupts are
enabled, a request is generated. TMRTRIG* can be connected to
selected internal signals on the RTSI bus with A4RCV set or the
external signal EXTTMRTRIG* with A4RCV cleared. In the polled I/O
mode, the TMRREQ signal must be monitored in the Status Register to
determine when the previous value has been updated to the DAC and a
new value is required. The most desirable solution involves the use of
interrupts because the PC is not dedicated to monitoring the Status
Register. If interrupts are enabled, an interrupt occurs when TMRREQ
is set. In interrupt mode, TMRREQ must be cleared using the TMRREQ