•
*
•
Signals with an * support digital filtering. Refer to the
section for more
information.
AI Convert Clock Signal Behavior For Analog Input Modules
section for more
information about AI Convert Clock signals and the cRIO controller.
AI Sample Clock Signal
A sample consists of one reading from each channel in the AI task. Sample Clock signals the
start of a sample of all analog input channels in the task. The sample clock can be generated
from external or internal sources as shown in the figure below.
Figure 34. AI Sample Clock Timing Options
Programmable
Clock
Divider
Sample Clock
Timebase
PFI
Analog Comparison Event
Ctr n Internal Output
AI Sample
Clock
Sigma-Delta Module Internal Output
Analog Comparison
Event
80 MHz Timebase
20 MHz Timebase
PFI
13.1072 MHz Timebase
12.8 MHz Timebase
10 MHz Timebase
100 kHz Timebase
Routing the Sample Clock to an Output Terminal
You can route Sample Clock to any output PFI terminal. Sample Clock is an active high pulse
by default.
AI Sample Clock Timebase Signal
The AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock.
AI Sample Clock Timebase can be generated from external or internal sources. AI Sample
Clock Timebase is not available as an output from the controller.
cRIO-904x User Manual
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© National Instruments
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