© National Instruments
|
6-27
cDAQ-9185/9189 User Manual
The counter ignores the Gate input while a pulse generation is in progress. After the pulse
generation is finished, the counter waits for another Start Trigger signal to begin another pulse
generation. For retriggered pulse generation, pause triggers are not allowed since the pause
trigger also uses the gate input.
Figure 6-29 shows a generation of two pulses with a pulse delay of five and a pulse width of
three (using the rising edge of Source) with
CO.EnableInitalDelayOnRetrigge
r set to the
default True.
Figure 6-29.
Retriggerable Single Pulse Generation with Initial Delay on Retrigger
Figure 6-30 shows the same pulse train with
CO.EnableInitalDelayOnRetrigger
set to the
default False.
Figure 6-30.
Retriggerable Single Pulse Generation False
Note
The minimum time between the trigger and the first active edge is two ticks
of the source.
For information about connecting counter signals, refer to the
Default Counter/Timer Routing
section.
Continuous Pulse Train Generation
This function generates a train of pulses with programmable frequency and duty cycle. The
pulses appear on the Counter
n
Internal Output signal of the counter.
You can specify a delay from when the counter is armed to the beginning of the pulse train. The
delay is measured in terms of a number of active edges of the Source input.
S
OURCE
GATE
(
S
t
a
rt Trigger)
OUT
5
3
5
3
Co
u
nter
Lo
a
d V
a
l
u
e
s
4
3
2 1 0 2 1 0
4
3
2
1
0 2 1
0
S
OURCE
GATE
(
S
t
a
rt Trigger)
OUT
5
3
2
3
Co
u
nter
Lo
a
d V
a
l
u
e
s
4
3
2 1 0 2 1 0
4
3
2 1 0 2 1 0
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