National Instruments AT-DIO-32F, User Manual

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Index
AT-DIO-32F User Manual Index-6 © National Instruments Corporation
RTSI Bus Register Group
overview, 4-26
RTSISHFT Register, 4-27, B-4
RTSISTRB Register, 4-28, B-4
sizes of, 4-3
status byte, B-5
REQ signal, 2-17
REQ1 bit, 4-17
REQ1 signal, 2-14
REQ2 bit, 4-17
REQ2 signal, 2-14
REVC bit, 4-15
RTSI bus clock configuration, 2-10 to 2-11
RTSI bus interface
default settings (chart), 2-2
programming, 4-53 to 4-55
theory of operation, 3-9
RTSI Bus Register Group
overview, 4-26
register map, 4-2
RTSISHFT Register, 4-27, B-4
RTSISTRB Register, 4-28, B-4
RTSI bus switch, programming
control patterns, 4-54
initializing, 4-55
overview, 4-53
switch signal connections, 4-54
RTSISHFT Register, 4-27, B-4
RTSISTRB Register, 4-28, B-4
RW<1..0> bit, 4-36
RWSEL<1..0> bit, 4-33 to 4-34
S
SETACK1 bit, 4-7
SETACK2 bit, 4-10
signal connections
descriptions of, 2-14 to 2-15
I/O connector pin description, 2-13
RTSI bus switch, 4-54
signals
input specifications, 2-16, A-1
output specifications, 2-16, A-1
timing signals, 2-16 to 2-18
specifications
I/O connector electrical
specifications, 2-16
Intel 8254 programmable interval timer,
D-19 to D-20
I/O connector electrical specifications
input signal, A-1
output signal, A-1
operating environment, A-2
physical, A-2
power requirements, A-2
storage environment, A-2
timing specifications, 2-16 to 2-18
transfer rates, A-1
STAT Register
description, 4-16 to 4-17, B-3
register map, 4-2
STATUS* bit, 4-35
status byte, 4-36, B-5
storage environment specifications, A-2
support, technical, vii
switch control patterns, RTSI, 4-54
switch settings. See jumper
and switch settings.
T
TCINTEN1 bit, 4-13
TDELAY signal, 2-17
technical support, xii
theory of operation
address decoder, 3-2
AT-DIO-32F block diagram, 3-1
bus transceivers, 3-2
configuration and status registers, 3-2
data latches and drivers, 3-2 to 3-3
digital I/O connector, 3-4
DMA control circuitry, 3-10
handshaking circuitry, 3-4 to 3-10
leading edge mode, 3-7 to 3-8
level mode, 3-5 to 3-6
trailing edge mode, 3-9 to 3-10
interrupt control circuitry, 3-10
onboard counters, 3-3
PC I/O channel control circuitry, 3-2
RTSI bus interface, 3-11
timing specifications
read and write timing, 2-19 to 2-20
signals for, 2-16 to 2-18
TIS<2..0> bit, 4-5
trailing edge mode. See handshaking.