National Instruments AT-DIO-32F, User Manual

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Programming Chapter 4
AT-DIO-32F User Manual 4-14 © National Instruments Corporation
CFG4 Register
Revision C and later versions of the AT-DIO-32F have a CFG4 Register. This register contains
four bits that set the leading pulse delay mode, Port D double-buffer mode, and version
compatibility.
Address: Base a 14 (hex)
Type: Write-only
Word Size: 16-bit
Bit Map:
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 LPULSE2 LPULSE1 DBLBUFD REVC
Bit Name Description
15-4 Reserved Bits.
These bits must be set to zero.
3 LPULSE2 Long Pulse Bit for Group 2.
This bit selects the data-settling delay mode of the leading-edge
pulse handshaking mode for Group 2. If this bit is set, the delay is
added after the leading edge of the ACK pulse; therefore, the pulse
width is lengthened. The delay is 0 to 700 nsec, depending on the
settings of T2S <2..0>. If this bit is cleared, the delay is added
before the leading edge of the pulse; therefore, the pulse width is
fixed.
2 LPULSE1 Long Pulse Bit for Group 1.
This bit selects the data-settling delay mode of the leading-edge
pulse handshaking mode for Group 1. If this bit is set, the delay is
added after the leading edge of the ACK pulse; therefore, the pulse
width is lengthened. The delay is 0 to 700 nsec, depending on the
settings of T1S <2..0>. If this bit is cleared, the delay is added
before the leading edge of the pulse; therefore, the pulse width is
fixed.