National Instruments AT-DIO-32F, User Manual

Page: 150 / 155

Index
AT-DIO-32F User Manual Index-2 © National Instruments Corporation
CNT1SRC bit, 4-12
CNT2EN bit, 4-13
CNT2HSEN bit, 4-13
CNT2SRC bit, 4-12
CNTINT bit, 4-16
CNTINTCLR Register
description, 4-18, B-3
register map, 4-2
CNTINTEN bit, 4-12
CNTINTEN2 bit, 4-13
CNTR<3..0> bit, 4-35
CNTR1B<7..0> bit, 4-30
CNTR2B<7..0> bit, 4-31
CNTR3B<7..0> bit, 4-32
CNTR1 Register (REQ1 generator)
description, 4-30, B-4
register map, 4-2
CNTR2 Register (REQ2 generator)
description, 4-31, B-4
register map, 4-2
CNTR3 Register (timebase generator)
description, 4-32, B-5
register map, 4-2
CNTRCMD Register
description, 4-33 to 4-36, B-5
register map, 4-2
CNTRSEL<1..0> bit, 4-33, 4-35
compatibility with I/O applications and
devices, 1-1 to 1-2
configuration
base I/O address selection, 2-4 to 2-7
AT bus interface, 2-1
DMA channel selection, 2-7 to 2-9
interrupt selection, 2-9 to 2-10
RTSI bus clock selection, 2-10 to 2-11
Configuration and Status Register Group
CFG1 Register, 4-5 to 4-7, B-2
CFG2 Register, 4-8 to 4-10, B-2
CFG3 Register, 4-11 to 4-13, B-2
CFG4 Register, 4-14 to 4-15, B-2
CNTINTCLR Register, 4-18, B-3
DMACLR1 Register, 4-19, B-3
DMACLR2 Register, 4-20, B-3
overview, 4-4
register map, 4-2
STAT Register, 4-16 to 4-17, B-3
theory of operation, 3-2
COUNT* bit, 4-35
Counter 1 and Counter 2
pattern generation, 4-50 to 4-52
Counter 3
pattern generation, 4-49 to 4-50
programming example, 4-47
Counter Register Group
CNTR1 Register (REQ1 generator),
4-30, B-4
CNTR2 Register (REQ2 generator),
4-31, B-4
CNTR3 Register (timebase generator),
4-32, B-5
CNTRCMD Register, 4-33 to 4-36, B-5
overview, 4-29
register map, 4-2
counters, onboard. See onboard counters.
customer communication, xii
D
data latches and drivers, 3-2 to 3-3
data-settling delay. See handshaking.
DATA signal, 2-18
DBLBUFA bit, 4-6
DBLBUFB bit, 4-11
DBLBUFC bit, 4-9
DBLBUFD bit, 4-15
DBLDMA bit, 4-12
digital I/O connector, 3-4
Digital I/O Port Register Group
overview, 4-21
Port A Register, 4-22, B-3
Port B Register, 4-23, B-3
Port C Register, 4-24, B-4
Port D Register, 4-25, B-4
register map, 4-2
DIOA0 through DIOA7 signals, 2-14
DIOAEN bit, 4-6
DIOB0 through DIOB7 signals, 2-14
DIOBEN bit, 4-6
DIOC0 through DIOC7 signals, 2-15
DIOCEN bit, 4-9
DIOD0 through DIOD7 signals, 2-15
DIODEN bit, 4-9
DMA channel
configuration, 2-7 to 2-9
default settings (chart), 2-2
default settings for National Instruments
products, 2-6
jumper settings, 2-8 to 2-9