NAGASAKI IPC
57
DMA Channel Map
The equivalent of two 8237A DMA controllers are implemented in the PC104-688VL
board. Each controller is a four-channel DMA device that will generate the memory
addresses and control signals necessary to transfer information directly between a
peripheral device and memory. This allows high speeding information transfer with less
CPU intervention. The two DMA controllers are internally cascaded to provide four
DMA channels for transfers to 8-bit peripherals (DMA1) and three channels for transfers
to 16-bit peripherals (DMA2). DMA2 channel 0 provides the cascade interconnection
between the two DMA devices, thereby maintaining IBM PC/AT compatibility.
The following is the system information of DMA channels:
DMA Controller 1
DMA Controller 2
Channel 0: Spare
Channel 4: Cascade for
controller 1
Channel 1: Reserved for
IBM SDLC
Channel 5: Spare
Channel 2: Diskette
adapter
Channel 6: Spare
Channel 3: Spare
Channel 7: Spare
Summary of Contents for PC104-688VL
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