MYiR FZ3, Hardware Manual

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FZ3 Deep Learning Accelerator Card
Hardware Manual
2.2 SoC BANK
Figure 2-2 XCZU3EG SFVC784 Banks

BANK 0 : humidity Sensor, XADC , Other configuration signals

BANK 24
：
PL HD BANK, 24Pin(12 pairs of differential signal)

BANK 25
：
PL HD BANK, 24Pin(12 pairs of differential signal)

BANK 26
：
PL HD BANK, 24Pin(12 pairs of differential signal)

BANK 44
：
PL HD BANK, 24Pin(12 pairs of differential signal)

BANK 64
：
PL HP BANK, 52Pin(26 pairs of differential signal)

BANK 65
：
PL HP BANK, 52Pin(26 pairs of differential signal)

BANK 66
：
PL HP BANK, 52Pin(26 pairs of differential signal)

BANK 500: PS side, MIO[00:25] 26pin
，
multiplex pin

BANK 501: PS side, MIO[26:51] 26pin
，
multiplex pin
 BANK 502: PS side, MIO[52:77] 26pin
，
multiplex pin

BANK 503: PS side, PS configuration pin, includeJTAG boot configuration reset, etc.
 BANK 504: PS side, DDR BANK

BANK 505: PS side, MGTR BANK