MYiR-Tech
|
www.myirtech.com
14
/
27
FZ3 Deep Learning Accelerator Card
Hardware Manual
3.6 USB
Figure 3-6
Zynq ’s PS-side USB controller is connected to a SMSC company ’s USB PHY chip
USB3320C to form a USB 2.0 port as a USB Host, and then expands four USB2.0 ports
through GL852G. One of the port signals is combined with the PS 3.0 USB port Together
form a USB3.0 port, and several other ports are led out as separate USB2.0 ports.
USB3320C is connected to the PS_MIO52 ~ PS_MIO63 pins of the USB0-BANK501 of
the CPU.
U35
PS_MIO52 USB0_CLK_IN
PS_MIO53 USB0_DIR
PS_MIO54 USB0_TX_D2
PS_MIO55 USB0_NXT
PS_MIO56 USB0_TX_D0
PS_MIO57 USB0_TX_D1
PS_MIO58 USB0_STP
PS_MIO59 USB0_TX_D3
PS_MIO60 USB0_TX_D4
PS_MIO61 USB0_TX_D5
PS_MIO62 USB0_TX_D6
PS_MIO63 USB0_TX_D7
PS_MIO38 USB0_RESET_N
Table 3-6
