5.1.6 PIP STATUS REGISTER 2
STAT2: port 80Bh
Bit Number
7
6
5
4
3
2
1
0
Function
DSW2_1
DSW2_2
DSW2_3
DSW2_4
DSW2_5
DSW2_6
DSW2_7
DSW2_8
Default
X
X
X
X
X
X
X
X
DSW2_8 to DSW2_1
(Read-Only)
These bits reflect the position of DIP switches SW2-1 to SW2-8. These DIP switches are used to select the
LVDS panel graphics mode.
5.1.7 PARALLEL PORT FLOPPY REGISTER
PPFLPY
: port 80Ch (Read / Write)
Bit Number
7
6
5
4
3
2
1
0
Function
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PPEN
Default
0
0
0
0
0
0
0
0
PPEN
(Read / Write)
This bit controls the Parallel Port Power.
PPEN
Function
0
Parallel port power (J3 pin 25) disabled (connected to Ground)
1
Parallel port power (J3 pin 25) enabled (connected to +5 V)
Please refer to the section 3.5.1.1 for the location of the parallel port power pin.
5.1.8 PIP FAMILY ID REGISTER
PIPID
: port 80Dh (Read-Only)
Bit Number
7
6
5
4
3
2
1
0
Function
PIPID7
PIPID6
PIPID5
PIPID4
PIPID3
PIPID2
PIPID1
PIPID0
Default
X
X
X
X
X
X
X
X
PIPID[7 to 0]
(Read-Only)
This register is used to identify the current PIP PCB Model and Revision
.
PIPID[7
to
0]
Function
B0h
PIP20 – PCB Rev. A
B1h
PIP20 – PCB Rev. B
...
...
C0h
PIP22 – PCB Rev. A
C1h
PIP22 – PCB Rev. B
...
D0h
PIP19 – PCB Rev. A
D1h
PIP19 – PCB Rev. B
...
E0h
PIP23 – PCB Rev. A
E1h
PIP23 – PCB Rev. B
...
2012 by MPL AG
52
MEH-10126-201 Rev. F
High-Tech • Made in Switzerland
PIP19 / PIP20 / PIP22 / PIP23
Technical Reference Manual
