Board Level Hardware Description
1-16
Installation Guide
1
3. Writes to the LCSR in the VMEchip2 must be 32 bits.
LCSR writes of 8 or 16 bits terminate with a TEA signal.
Writes to the GCSR may be 8, 16, or 32 bits. Reads to the
LCSR and GCSR may be 8, 16, or 32 bits.
4. This area does not return an acknowledge signal. If the
processor bus timeout timer is enabled, the access times
out and is terminated by a TEA signal.
5. Size is approximate.
6. Port commands to the 82596CA must be written as two
16-bit writes: upper word first and lower word second.
7. DROM (BOOT ROM) appears at $0 following a local
peripheral bus reset. The DROM appears at 0 until the
DR0 bit is cleared in the PCCchip2. The DR0 bit is
located at address 0 bit D15. The DROM must be
disabled at 0 before the DRAM is accessed.
VMEbus Memory Map
This section describes the mapping of local resources as viewed by VMEbus
masters.
VMEbus Accesses to the Local Peripheral Bus
The VMEchip2 includes a user-programmable map decoder for the VMEbus
to local peripheral bus interface. The map decoder allows the user to program
the starting and ending address and the modifiers the MVME197LE responds
to.
VMEbus Short I/O Memory Map
The VMEchip2 includes a user-programmable map decoder for the GCSR
(Global Control and Status Registers). The GCSR map decoder allows the user
to program the starting address of the GCSR in the VMEbus short I/O space.
Solution Systems Technologies Inc.
720-565-5995 | [email protected] | www.solusys.com
Solution Systems Technologies Inc.
720-565-5995 | [email protected] | www.solusys.com
