Motorola MC68838, User Manual

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MOTOROLA MC68838 USER’S MANUAL 5-3
5.3 WRITE CYCLE
The NP uses a write cycle to write data into a MAC register (see Figure 5-2). It is similar
to the read cycle previously described. The principal differences are as follows:
1. The NPRW line must be low a setup time before, and a hold time after, the first
rising edge of NPCLK after
MACSEL is asserted, and
2. The data to be written must be valid a setup time before, and a hold time after, the
second rising edge of NPCLK after MACSEL is asserted.
The host bus logic can assert MACSEL to introduce as many wait states as necessary.
Like the MAC, the NP must three-state the NPDx bus within 40 ns after the second rising
edge of NPCLK after
MACSEL is negated. Thus, by delaying the negation of MACSEL,
the NP can extend the time it has to three-state the NPDx bus. The negation of MACSEL
has no effect on the MAC in a write cycle. See 5.2 Read Cycle for more details.
NPD
CS
NPRW
NPA
BYTCLK (NPCLK)
Figure 5-2. Node Processor Bus Write Cycles
ARCHIVE INFORMA
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ARCHIVE INFORMA
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