Motorola MC68838, User Manual

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MOTOROLA MC68838 USER’S MANUAL 3- 23
3.3.3 Interrupt Event Register C (INTR_EVENT_C)
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 VOID_TIMER_
REG_RDY
VOID_TIMER _
OVF
TKN_CNT_OVF
Bits 15–3—These bits are reserved and should be set to zero.
VOID_TIMER_REG_RDY—Void Timer Register Ready
This bit is set when the void timer loads the void time register with a new count.
VOID_TIMER_REG_RDY indicates that a new timing of the ring latency was done and
the void time register contains the updated latency time.
VOID_TIMER_OVF—Void Timer Overflow Bit
This bit is set when the void timer count exceeds 64K, causing the timer to wrap around.
Thus, the void time register will not be loaded. This bit can indicate configuration
problems in the ring.
TKN_CNT_OVF—Token Counter Overflow Bit
This bit is set when the token counter exceeds 64K. The token counter wraps around to
zero and continues to count. This bit indicates that the token count value is not accurate
because there is no way of determining how many times the counter has wrapped.
3.3.4 Interrupt Mask Register A (INTR_MASK_A)
This register implements part of the interrupt mask register corresponding to interrupt
mask register A. Each interrupt mask register corresponds bit for bit with the interrupt
event register. When a bit in this register is set and the corresponding bit in the interrupt
event register is also one, an interrupt is generated. This register is only read by the MAC
chip. lt can be read and written by the NP at any time. lt is cleared on power-up reset and
unaffected by a MAC_RESET.
3.3.5 Interrupt Mask Register B (INTR_MASK_B)
This register implements part of the interrupt mask register corresponding to interrupt
mask register B. Each interrupt mask register corresponds bit for bit with the interrupt
event register. When a bit in this register is set and the corresponding bit in the interrupt
event register is also one, an interrupt is generated. This register is only read by the MAC
chip. lt can be read and written by the NP at any time. lt is cleared on power-up reset and
is unaffected by a MAC_RESET.
3.3.6 Interrupt Mask Register C (INTR_MASK_C)
This register implements part of the interrupt mask register corresponding to interrupt
mask register C. Each interrupt mask register corresponds bit for bit with the interrupt
ARCHIVE INFORMA
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ARCHIVE INFORMA
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