0.1UF
C6
W2
+
25V
10UF
C1
TANT
+
25V
10UF
C11
TANT
+
25V
10UF
C12
TANT
+
25V
10UF
C2
TANT
VSSI
VDDI
L5
1UH
L4
E1
VSSA
0.1UF
C17
VDDA
VSSA
VSSA
W4
VSSA
0.1UF
C8
VDDA
W3
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
L1
GND
+5V
1UH
L2
0.1UF
C65
0.1UF
C59
VSSI
VDDI
GND
GND
GND
GND
GND
GND
+5V
0.1UF
C54
0.1UF
C3
GND
0.1UF
C56
0.1UF
C4
GND
0.1UF
C58
GND
0.1UF
C5
0.1UF
C61
GND
0.1UF
C51
0.1UF
C63
GND
0.1UF
C52
0.1UF
C64
GND
0.1UF
C53
A
REV:
DWG. NO.
SIZE
GEDABV:
SHEET
DWG. NO.
REV:
GEDTTL:
A
D
31
2
C
B
4
A
D
C
31
2
4
MPB334B
3 OF 8
O
63ASE90534W
LAST_MODIFIED=Mon Aug 1 17:36:28 1994
BOARD
63ASE90534W
O
0.01UF
C13
0.01UF
C7
0.01UF
C9
0.01UF
C10
0.01UF
C16
0.01UF
C15
0.01UF
C14
BYPASS CAPACITORS, CLEAN POWER & SIGNAL FILTERS
(CUT TRACE ON BOARD)
ANALOG SIGNAL FILTERS
ADC MODULE
VDDA/VSSA GENERATION
ADC MODULE
VDDI/VSSI GENERATION
+5V AND GND DECOUPLING
FOR VDDE OF MCU AND OSCILLATOR
VRH & VRL SELECTION
ADC MODULE
2
1
AN<6..0>
2
1
FERRITE BEAD
FERRITE BEAD
VRL
MAPI-VRL
VRH
MAPI-VRH
AN<2>
AN<0>
AN<1>
AN<3>
AN<4>
AN<5>
AN<6>
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
12
12
12
12
1
1 2
3
1 2
3
1
2
1
2
1
2
1
2
4C1> 5B1>
6B1<
4C1>
6B1<
5B1>