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MEVB SUPPORT INFORMATION

4-2

M68MPB334UM/D

Table 4-1. Logic Analyzer Connector J7 Pin Assignments

Pin

Mnemonic

Signal

1, 2

SPARE

No connection

OE(ALL)

I/O PRU OUTPUT ENABLE – Input, active high; when
low disables

all

PRU outputs.

4 – 11

PEPAR7 –

PEPAR0

PEPAR OUTPUTS – Output signals that show the

complement

(negated contents) of the PEPAR register.

12 – 19

PE7 – PE0

PORT E I/O SIGNALS – PRU replacement of the port
E function.

GND

GROUND

Table 4-2. Logic Analyzer Connector J8 Pin Assignments

Pin

Mnemonic

Signal

1, 2

SPARE

No connection

OE(ABG)

I/O PRU OUTPUT ENABLE – Input, active high; when
low disables port A, port B, and port G outputs.

4 – 11

PA7 – PA0

PORT A I/O SIGNALS – PRU replacement of the port
A function.

12 – 19

PB7 – PB0

PORT B I/O SIGNALS – PRU replacement of the port
B function.

GND

GROUND

Summary of Contents for M68MPB334

Page 2: ... the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of direct...

Page 3: ...r W3 2 6 2 2 4 Voltage Reference Low Select Header W4 2 7 2 2 5 VSSA Insertion Point E1 2 7 2 3 MEVB CONFIGURATION 2 8 2 4 ACTIVE PROBE CONFIGURATION 2 10 CHAPTER 3 MEVB QUICK START GUIDE 3 1 INTRODUCTION 3 1 3 2 CONFIGURING THE MPFB 3 1 3 2 1 MPFB Memory Devices 3 1 3 2 2 MPFB Jumper Headers 3 2 3 3 MEVB INSTALLATION INSTRUCTIONS 3 3 3 3 1 Power Supply MPFB Connection 3 3 3 3 2 Personal Computer ...

Page 4: ...ssignments 5 4 5 5 MAPI Interface Connector P4 Pin Assignments 5 5 TABLES 1 1 MPB Specifications 1 2 2 1 Jumper Header Types 2 3 2 2 MPB Jumper Header Descriptions 2 3 3 1 MPFB Quick Start Jumper Header Configuration 3 2 4 1 Logic Analyzer Connector J7 Pin Assignments 4 2 4 2 Logic Analyzer Connector J8 Pin Assignments 4 2 4 3 Logic Analyzer Connector J9 Pin Assignments 4 3 4 4 Logic Analyzer Conn...

Page 5: ...ES continued 4 11 Logic Analyzer Connector J17 Pin Assignments 4 9 4 12 Logic Analyzer Connector J18 Pin Assignments 4 10 4 13 Logic Analyzer Connector J19 Pin Assignments 4 10 4 14 Logic Analyzer Connector J20 Pin Assignments 4 11 ...

Page 6: ...CONTENTS vi M68MPB334UM D ...

Page 7: ...MMDS or the M68MEVB1632 Modular Evaluation Board MEVB Alternately you may install the MPB directly in your target system if the target system includes a modular active probe interconnect MAPI interface The MCU device on the MPB defines which MCU is emulated evaluated by the MMDS or MEVB Both systems are invaluable tools for designing debugging and evaluating MCU operation of the M68HC16 and M68300...

Page 8: ...tible Temperature Operating Storage 0 to 40 C 40 to 85 C Relative humidity 0 to 90 non condensing Power requirements 5Vdc 5 500 mA max Dimensions MCU Personality Board 3 25 x 3 25 in 82 6 x 82 6 mm 1 3 EQUIPMENT REQUIRED The external requirements for MPB operation are either an MPFB or MMDS system For MMDS operation requirements see the MMDS1632 Motorola Modular Development System User s Manual MM...

Page 9: ...852 6106888 Tai Po 852 6668333 INDIA Bangalore 91 80 5598615 ISRAEL Herzlia 972 9 590222 ITALY Milan 39 2 82201 JAPAN Fukuoka 81 92 725 7583 Gotanda 81 3 5487 8311 Nagoya 81 52 232 3500 Osaka 81 6 305 1802 Sendai 81 22 268 4333 Takamatsu 81 878 37 9972 Tokyo 81 3 3440 3311 KOREA Pusan 82 51 4635 035 Seoul 82 2 554 5118 MALAYSIA Penang 60 4 2282514 MEXICO Mexico City 52 5 282 0230 Guadalajara 52 36...

Page 10: ...GENERAL INFORMATION 1 4 M68MPB334UM D ...

Page 11: ...ration This section also explains MPB installation in the MMDS and MEVB The MPB has been factory tested and is shipped with installed jumpers A jumper installed on a jumper header provides a connection between two points in the MPB circuit There are two types of jumper headers on the MPB three pin and two pin with a cut trace short A cut trace short has a copper trace between the feed through hole...

Page 12: ...iring trace short cut trace short Be careful not to cut adjacent PCB traces nor cut too deep into the multi layer circuit board If the cut trace short on a jumper header is already cut you can return the MPB to its default setting by installing a user supplied fabricated jumper Figure 2 1 M68MPB334 Parts Location Diagram top view ...

Page 13: ...Jumper between pins 1 and 2 factory default selects the MPB on board crystal clock source Jumper between pins 2 and 3 selects an external clock sourceto be the MCU EXTAL input signal W2 1 2 Jumper installed or cut trace short intact factory default selects the on board VDDA power source No jumper or cut trace short lets you connect an external power source to W2 pin 2 and the external power source...

Page 14: ...CU allows via the internal phase locked loop or direct clock input If you install the MPB in the active probe or directly on a target system and use the target system clock as the MPB clock move the fabricated jumper to W1 pins 2 and 3 This connects the MCU EXTAL pin to the MAPI bus input pin The frequency of the external clock signal can be from 32 kHz to 16 78 MHz or to the maximum the MCU allow...

Page 15: ...ternal power source to W2 pin 2 Removal of the cut trace short isolates the MCU VDDA pin from the other MPB circuitry Isolation lets you connect a precision VDDA source for accurate 10 bit analog digital A D generation When connecting an external VDDA power supply to the MPB connect the power supply ground to insertion point E1 For more information on A D generation refer to the Analog To Digital ...

Page 16: ...fabricated jumper on W3 pins 2 and 3 Then connect the MCU VRH pin to the external VRH source Each configuration defines the best method for connecting the MCU VRH pin to the external VRH source MPB MPFB connect via the MPFB logic analyzer connector refer to Chapter 4 for the appropriate logic analyzer pin MPB MMDS1632 connect via the VRH pin of the target MCU socket MPB Target System connect via t...

Page 17: ...ng the MCU VRL pin to the external VRL source MPB MPFB connect via the MPFB logic analyzer connector refer to Chapter 4 for the appropriate logic analyzer pin MPB MMDS1632 connect via the VRL pin of the target MCU socket MPB Target System connect via the VRL pin of the target system MAPI bus Alternately you may remove the jumper and wire wrap directly to W4 pin 2 Connecting directly to pin 2 is an...

Page 18: ... help you get started using your MEVB CAUTION Turn OFF MPFB power when installing the MPB on the MPFB or removing the MPB from the MPFB Sudden power surges could damage MEVB integrated circuits To install the MPB on the MPFB refer to Figure 2 2 1 Inspect all connectors for bent or damaged pins 2 Align the MPB reference mark with the MPFB reference mark 3 Rotate the MPB until the four MAPI bus conn...

Page 19: ...connection with SDI Interface After you have installed the MPB install the plastic overlay on the MPFB place the overlay over logic analyzer connectors J12 through J20 and press down Holes in the overlay slide down over plastic clips on the MPFB These clips hold the overlay in place ...

Page 20: ...active probe and the station module 01 RE90340W01 REV 0 and 01 RE90341W01 REV 0 are printed on the active probe cables The active probe cables come with the MMDS For more information about the active probe cables refer to the M68MMDS1632 Motorola Modular Development System User s Manual MMDS1632UM D Active probe box the protective enclosure for the TCB CAUTION Turn off MMDS and target system power...

Page 21: ...end of the 01 RE90340W01 REV 0 active probe cable to connector P5 on the MMDS control board connect the other end to connector J5 on the TCB Secure the connector clamps on TCB connectors J5 and J6 The active probe is now ready to connect to the target system refer to the PPB configuration guide for information on connecting the active probe to the target system Figure 2 3 Active Probe Interconnect...

Page 22: ...HARDWARE PREPARATION AND INSTALLATION 2 12 M68MPB334UM D ...

Page 23: ...ns the default jumper header settings for the MPB 3 2 CONFIGURING THE MPFB The MPFB includes jumper selectable options such as chip select usage memory type selection and memory size selection for the pseudo ROM sockets and reset data control NOTE The MPFB must be configured for the specific MPB Paragraph 3 2 2 provides a configuration for basic MPFB operation For a detailed description of the MPF...

Page 24: ...sable the PRU W10 1 3 5 2 4 6 Install a jumper on pins 1 and 2 to indicate that RAM is installed in the pseudo ROM sockets U2 U4 W12 1 3 5 7 9 2 4 6 8 10 Install a jumper on pins 3 and 4 to indicate that the two devices installed in the pseudo ROM sockets U2 U4 are 32K x 8 W14 1 2 3 Jumper header W14 selects the MCU signal for the memory devices in the fast RAM sockets U9 U10 and pseudo ROM socket...

Page 25: ...and host computer The host computer must have a parallel port and must run MS DOS as required by ICD32 The following paragraphs explain MPFB connections Refer to Chapter 2 for instructions to connect the MPB and MPFB 3 3 1 Power Supply MPFB Connection Use MPFB connector J5 Figure 3 1 to connect a user supplied power supply to the MEVB Contact 1 is ground black lever Contact 2 is VDD 5 volts red le...

Page 26: ...igure 3 1 MPFB Power Supply Connector CAUTIONS Do not use wire larger than 20 AWG in connector J5 Such wire could damage the connector Turn off MEVB power when installing or removing the MPB from the MPFB Sudden power surges could damage MEVB integrated circuits ...

Page 27: ...nect your BDM hardware between your computer s I O port and the BDM header on the MPFB MPFB connector J6 The drawing below shows signal assignments for connector J6 For additional information about your BDM software hardware including debugging and assembly information see the appropriate user s manual J6 DS 1 2 BERR GND 3 4 BKPT GND 5 6 FREEZE RESET 7 8 DSI 5 Vdc 9 10 DSO ...

Page 28: ...alized before the MEVB will function The following is one possible initialization for the MPB334 You may adapt this example to your debugger This initialization enables the maximum system clock frequency and disables the software watchdog while enabling the bus monitor CSBOOT is set to zero wait state and the block size set to 64K starting at 00000 A7 is initialized at 10700 and the program counte...

Page 29: ... TRAMBAR FFFB04 TPU RAM Base Address Register High mdf3 200 Display memory at 200 to stop bus errors var w CSORBT Show variables in F6 area var w CSBARBT var w SIMCR var w SYNCR pc 200 Temporarily set program counter stack pointer a7 200 to stop bus errors mm w SIMCR 40CF Set Module Mapping to FFF000 FFFFFF mm b SYNCR 7F Set System Clock Frequency to 16 78 MHz watchdog Disable watchdog timer mm w ...

Page 30: ... 1051C 52414D20 Sample program for code window asm START addi w AAAA D0 clr l D0 addi w AAAA D1 clr l D1 addi w AAAA D2 clr l D2 addi w AAAA D3 clr l D3 bra b 10400 NOP NOP NOP NOP NOP NOP NOP NOP NOP mdf3 START Display example code in F3 area mdf6 MESSAGE Display MESSAGE in F6 area asciiF6 Show F6 area as ASCII characters MPFB1632 RAM CSBOOT 000000 00ffff MCU TPU RAM 010400 0107FF See MPB User s ...

Page 31: ...he MPB type 4 2 LOGIC ANALYZER CONNECTOR SIGNALS The tables of this chapter describe MPFB logic analyzer connector signalsif you install an M68MPB334 on the MPFB The signal descriptions on J12 J20 are the logic analyzer pin outs on the plastic overlay supplied with the MPB NOTE The signal descriptions in the following tables are for quick reference only The MC68334 User s Manual MC68334UM AD conta...

Page 32: ...omplement negated contents of the PEPAR register 12 19 PE7 PE0 PORT E I O SIGNALS PRU replacement of the port E function 20 GND GROUND Table 4 2 Logic Analyzer Connector J8 Pin Assignments Pin Mnemonic Signal 1 2 SPARE No connection 3 OE ABG I O PRU OUTPUT ENABLE Input active high when low disables port A port B and port G outputs 4 11 PA7 PA0 PORT A I O SIGNALS PRU replacement of the port A funct...

Page 33: ... G I O SIGNALS PRU replacement of the port G function 20 GND GROUND Table 4 4 Logic Analyzer Connector J10 Pin Assignments Pin Mnemonic Signal 1 5V 5 VDC POWER Input voltage 5Vdc 1 0 A used by the MEVB logic circuits To make this pin a no connection remove the jumper from jumper header W9 on the MPFB 2 SPARE No connection 3 AS ADDRESS STROBE Active low output signal that indicates whether a valid ...

Page 34: ...Logic Analyzer Connector J12 Pin Assignments Pin Mnemonic Signal 1 2 SPARE No connection 3 CLKOUT SYSTEM CLOCK OUT Output signal that is the MCU internal system clock 4 BERR BUS ERROR Active low signal that indicates a memory access error has occurred 5 BKPT DSCLK BREAKPOINT Active low input signal that signals a hardware breakpoint to the CPU Development Serial Clock Clock input signal for backgr...

Page 35: ...ic bus sizing between the MCU and external devices 12 DSACK0 DATA AND SIZE ACKNOWLEDGE 0 Active low input signal that allows asynchronous data transfers and dynamic bus sizing between the MCU and external devices 13 FC2 CS5 FUNCTION CODE 2 Output signal that identifies the processor state and address space of the current bus cycle CHIP SELECT 5 Output signal that selects peripheral or memory devic...

Page 36: ...emory devices at programmed addresses 20 GND GROUND Table 4 7 Logic Analyzer Connector J13 Pin Assignments Pin Mnemonic Signal 1 5V 5 VDC POWER Input voltage 5Vdc 1 0 A used by the MEVB logic circuits To make this pin a no connection remove the jumper from jumper header W21 on the MPFB 2 SPARE No connection 3 DSACK1 DATA AND SIZE ACKNOWLEDGE 1 Active low input signal that allows asynchronous data ...

Page 37: ...at selects peripheral or memory devices at programmed addresses 10 CSBOOT BOOT CHIP SELECT An active low output chip select for external boot startup ROM 11 CLKOUT SYSTEM CLOCK OUTPUT MCU internal clock output signal 12 A23 CS10 ADDRESS BUS BIT 23 One bit of the 24 bit address bus CHIP SELECT 10 Output signal that selects peripheral or memory devices at programmed addresses 13 A22 CS9 ADDRESS BUS ...

Page 38: ...ection 3 DSACK0 DATA AND SIZE ACKNOWLEDGE 0 Active low input signal that allows asynchronous data transfers and dynamic bus sizing between the MCU and external devices 4 MODCLK CLOCK MODE SELECT Input signal that configures the MCU internal clock at reset 5 TSC THREE STATE CONTROL When TSC is logic high this input signal forces all output drivers to a high impedance state 6 RESET RESET Active low ...

Page 39: ...UNIT CHANNELS TPU input output channels 17 GND GROUND 18 19 SPARE No connection 20 GND GROUND Table 4 10 Logic Analyzer Connector J16 Pin Assignments Pin Mnemonic Signal 1 4 SPARE No connection 5 12 TPU0 TPU7 TIME PROCESSOR UNIT CHANNELS TPU input output channels 13 19 SPARE No connection 20 GND GROUND Table 4 11 Logic Analyzer Connector J17 Pin Assignments Pin Mnemonic Signal 1 4 SPARE No connect...

Page 40: ... reference supply voltage high line must set jumper on the MPB 13 VRL VOLTAGE REFERENCE LOW Input reference supply voltage low line must set jumper on the MPB 14 15 AN5 AN6 ANALOG INPUT 5 6 Analog input line to the MCU device 16 VSSA A D GROUND A D ground reference 17 19 SPARE No connection 20 VSSA A D GROUND A D ground reference Table 4 13 Logic Analyzer Connector J19 Pin Assignments Pin Mnemonic...

Page 41: ...emonic Signal 1 4 SPARE No connection 5 GND GROUND 6 12 IRQ1 IRQ7 TARGET INTERRUPT REQUEST 1 7 Active low input signals from the target that asynchronously provides an interrupt priority level to the CPU IRQ1 has the lowest priority IRQ7 has the highest 13 18 GND GROUND 19 SPARE No connection 20 GND GROUND ...

Page 42: ...MEVB SUPPORT INFORMATION 4 12 M68MPB334UM D ...

Page 43: ...ter show the MAPI interface connector layout and pin assignments for MPB connectors P1 P2 P3 and P4 Figures 5 1 through 5 5 5 2 MAPI BUS CONNECTORS The connectors required to interface to the MAPI bus are 2 Robinson Nugent 2 X30 plugs P50L 060P AS TGF 2 Robinson Nugent 2 X40 plugs P50L 080P AS TGF 2 500 1 250 2 500 1 250 C L 1 1 1 1 C L C L C L C L C L Figure 5 1 MAPI Interface Connector Layout ...

Page 44: ...TPUCH11 35 n n 36 GND TPUCH12 37 n n 38 GND TPUCH13 39 n n 40 GND TPUCH14 41 n n 42 GND TPUCH15 43 n n 44 GND GND 45 n n 46 GND T2CLK 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 GND A23 CS10 E 55 n n 56 GND A22 CS9 PC6 57 n n 58 GND A21 CS8 PC5 59 n n 60 GND A20 CS7 PC4 61 n n 62 GND A19 CS6 PC3 63 n n 64 GND FC2 CS5 PC2 65 n n 66 GND FC1 CS4 PC1 67 n n 68 GND FC0 CS3 PC0 69 n ...

Page 45: ... 21 n n 22 A2 A3 23 n n 24 A4 A5 25 n n 26 A6 A7 27 n n 28 A8 A9 29 n n 30 GND A10 31 n n 32 A11 A12 33 n n 34 A13 A14 35 n n 36 A15 A16 37 n n 38 A17 A18 39 n n 40 GND No Connect 41 n n 42 5V GND 43 n n 44 GND VSSA 45 n n 46 VSSA VSSA 47 n n 48 VSSA VSSA 49 n n 50 AN0 VSSA 51 n n 52 AN1 VSSA 53 n n 54 AN2 VSSA 55 n n 56 AN3 VSSA 57 n n 58 AN4 VSSA 59 n n 60 MAPI VRH Figure 5 3 MAPI Interface Conn...

Page 46: ...GND GND 35 n n 36 GND GND 37 n n 38 IRQ7 PF7 GND 39 n n 40 IRQ6 PF6 GND 41 n n 42 IRQ5 PF5 GND 43 n n 44 IRQ4 PF4 GND 45 n n 46 IRQ3 PF3 GND 47 n n 48 IRQ2 PF2 GND 49 n n 50 IRQ1 PF1 GND 51 n n 52 GND GND 53 n n 54 VSTBY GND 55 n n 56 DSO IPIPE GND 57 n n 58 DSI IFETCH GND 59 n n 60 HALT GND 61 n n 62 RESET GND 63 n n 64 BERR GND 65 n n 66 BKPT DSCLK GND 67 n n 68 TSC GND 69 n n 70 FREEZE QUOT GND...

Page 47: ... GND DSACK0 PE0 25 n n 26 GND DSACK1 PE1 27 n n 28 GND AVEC PE2 29 n n 30 GND RMC PE3 31 n n 32 GND DS PE4 33 n n 34 GND AS PE5 35 n n 36 GND SIZ0 PE6 37 n n 38 GND SIZ1 PE7 39 n n 40 GND R W 41 n n 42 GND MODCLK PF0 43 n n 44 GND GND 45 n n 46 GND GND 47 n n 48 GND GND 49 n n 50 GND GND 51 n n 52 GND GND 53 n n 54 GND GND 55 n n 56 GND GND 57 n n 58 GND 5V 59 n n 60 No Connect Figure 5 5 MAPI Int...

Page 48: ...MAPI SUPPORT INFORMATION 5 6 M68MPB16Y3UM D ...

Page 49: ...6 1 CHAPTER 6 SCHEMATIC DIAGRAMS 6 1 INTRODUCTION This chapter contains the M68MPB916R3 MCU Personality Board MPB schematic diagrams These schematic diagrams are for reference only and may deviate slightly from the circuits on your MPB ...

Page 50: ...E REVISITION STATUS 1 TABLE OF CONTENTS OR CIRCUIT DESCRIBED HEREIN APPLICATION OR USE OF ANY PRODUCT MOTOROLA DOES NOT ASSUME ANY RELIABILITY FUNCTION OR DESIGN ANY PRODUCTS HEREIN TO IMPROVE CHANGES WITHOUT FURTHER NOTICE TO LIABILITY ARISING OUT OF THE MOTOROLA RESERVES THE RIGHT TO MAKE 6501 WILLIAM CANNON DRIVE WEST AUSTIN TEXAS 78735 USA MICROPROCESSOR AND MEMORY DRAWN BY DATE TECHNOLOGIES G...

Page 51: ... 2 INTERRUPTED LINES CODED WITH THE 3 DEVICE TYPE NUMBER IS FOR REFERENCE 4 SPECIAL SYMBOL USAGE 5 INTERPRET DIAGRAM IN ACCORDANCE 6 CODE FOR SHEET TO SHEET REFERENCES INPUT OUTPUT REVISION WITH THE EXCEPTION OF INSTITUTE SPECIFICATIONS CURRENT WITH AMERICAN NATIONAL STANDARDS DENOTES VECTORED SIGNALS DENOTES ACTIVE LOW SIGNAL ONLY THE NUMBER VARIES WITH THE LOGIC BLOCK SYMBOLOGY MANUFACTURER C7 5...

Page 52: ... 4 A D C 3 1 2 4 MPB334B 3 OF 8 O 63ASE90534W LAST_MODIFIED Mon Aug 1 17 36 28 1994 BOARD 63ASE90534W O 0 01UF C13 0 01UF C7 0 01UF C9 0 01UF C10 0 01UF C16 0 01UF C15 0 01UF C14 BYPASS CAPACITORS CLEAN POWER SIGNAL FILTERS CUT TRACE ON BOARD ANALOG SIGNAL FILTERS ADC MODULE VDDA VSSA GENERATION ADC MODULE VDDI VSSI GENERATION 5V AND GND DECOUPLING FOR VDDE OF MCU AND OSCILLATOR VRH VRL SELECTION ...

Page 53: ...C 3 1 2 4 MPB334B 4 OF 8 O 63ASE90534W LAST_MODIFIED Mon Aug 1 18 04 14 1994 BOARD 63ASE90534W O 5V GND GND 5V GND GND GND 5V MODULAR ACTIVE PROBE INTERCONNECT P1 P3 MAPI BUS P3 MAPI BUS P1 VSTBY DSO HALT DSI BERR RESET BKPT TSC FREEZE CLKOUT MAPI EXTAL NC CS 9 CS 10 CS 7 CS 8 CS 5 CS 4 CS 6 CS 2 CS 3 CS 1 CS 0 CS 10 0 CSBOOT T2CLK TPU 0 TPU 1 TPU 2 TPU 3 TPU 4 TPU 5 TPU 6 TPU 7 TPU 8 TPU 9 TPU 10...

Page 54: ...1 2 C B 4 A D C 3 1 2 4 MPB334B 5 OF 8 O 63ASE90534W LAST_MODIFIED Mon Aug 1 18 05 24 1994 BOARD 63ASE90534W O MAPI BUS P4 MAPI BUS P2 MODULAR ACTIVE PROBE INTERCONNECT P2 P4 A 2 A 4 A 8 A 6 A 11 A 13 A 17 A 15 NC A 1 A 3 A 5 A 7 A 9 A 10 A 12 A 14 A 18 A 16 NC A 0 D 10 D 8 D 14 D 12 D 1 D 7 D 5 D 3 D 15 D 11 D 13 D 2 D 0 D 4 D 6 D 9 NC DSACK0 DSACK1 AVEC RMC DS AS SIZ1 SIZ0 MODCLK R W D 15 0 A 18...

Page 55: ...CKET MC68334 U1 1UH L3 0 1UF C60 MCU CLOCK 2 THE CAP BETWEEN XFC VSSI IS OPTIONAL NOTE 1 PLACE THE CAP BETWEEN VDDSYN XFC AS CLOSE TO MCU PINS AS POSSIBLE 8 OR 14 PIN CANS DIPS 14 PIN DIP SOCKET FOR IRQ 7 1 RESET HALT SIZ1 CLKOUT BERR R W AVEC RMC DS AS SIZ0 DSACK0 DSACK1 11 8 2 1 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 10...

Page 56: ...68334 MCU PERSONALITY CODE 084HEX IRQ 2 IRQ 1 IRQ 5 IRQ 6 IRQ 7 IRQ 4 IRQ 3 NC NC NC NC NC NC TPU 1 TPU 4 TPU 10 TPU 9 TPU 11 TPU 12 TPU 15 TPU 13 TPU 14 TPU 6 TPU 5 TPU 3 TPU 2 TPU 0 T2CLK TPU 8 TPU 7 MODCLK NC NC A 4 A 5 A 6 A 7 NC NC NC NC NC A 1 A 2 A 9 A 10 A 8 A 3 IRQ 7 1 TPU 15 0 A 18 0 1M 7 16 6 5 4 3 1 2 8 9 10 11 12 13 14 15 1M 14 16 15 13 12 11 10 9 8 1 2 3 4 5 6 7 1 2 220K 6 16 9 5 10 ...

Page 57: ...AN 6 0 3B1 4C1 5B1 6B1 A 18 0 5D4 6D1 7D1 for the entire design Signal Cross Reference VSTBY 4B1 6C1 VRL 3B4 6B1 VRH 3B4 6B1 DSI 4B1 6D1 DSO 4B1 6D1 FREEZE 4A1 6D1 IRQ 7 1 4C1 6D4 7B4 MAPI EXTAL 4A1 6B1 MAPI VRH 3B4 5B1 MAPI VRL 3B4 4C1 MODCLK 5B4 6D4 7C4 D 15 0 5C4 6D4 DS 5C4 6D4 DSACK0 5C4 6D4 DSACK1 5C4 6D4 HALT 4B1 6C4 TSC 4B1 6D1 TPU 15 0 4C4 6B4 7C4 T2CLK 4B4 6B4 7B4 SIZ1 5C4 6C4 SIZ0 5C4 6D...

Page 58: ...SCHEMATIC DIAGRAMS 6 10 M68MPB334UM D ...

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