M68360QUADS-040 Hardware User’s Manual
FUNCTIONAL DESCRIPTION
29
FIGURE 4-1 Arbitration Scheme:
Since the level of priority associated with the BR~ input is lower (8) than the SDMA’s, no use is done with
the BCLRO~ signal of the QUICC is not used. In sake of simplicity, no use is done with the IPEND~ is not
used as a BCLI~ for the QUICC.
4.5
System Utilities
The slave QUICC provides the M68360QUADS-040 with the following system utilities, usually provided by
external logic:
1.
Breakpoint generation
2.
Bus Monitor (also known as hardware watch-dog)
3.
Spurious Interrupt Monitor
4.
Software watch-dog
5.
Periodic Interval Timer (also known as real-time-clock or tic-timer)
4.5.1
Breakpoints Generator
The QUICC may be used as a hardware breakpoint generator for the 68EC040. When the 68EC040
initiates a bus cycle by asserting TS~, the breakpoint logic compares the cycle’s address to the address in
the BKAR and to the access attributes in the BKCR. If there is a match, the BKPTO* signal is asserted by
the QUICC. Since TS~ is asserted only at the beginning of the cycle, no address comparison is done for
the rest of the access (burst access). The BKPTO* of the slave QUICC is wired via a jumper to generate
a non-maskable interrupt on level 7.
If the EC040 performs a breakpoint instruction, the QUICC will not respond, letting the bus monitor
terminate the cycle with TEA~.
4.5.2
Bus Monitor
The QUICC monitors for unterminated bus cycles, performed either by the 68EC040 or by the QUICC’s
internal masters. If a bus cycle fails to terminate with TA~ or TEA~ (DSACK~ or BERR) during a
programmable period of time, the bus monitor terminates the cycle, by asserting TEA~ for the EC040 (or
BERR~ for an internal master). Upon reset, the bus monitor is initialized to expire after 1K system clocks
(CLKO1 clocks).
QUICC
EC040
BR
BG
BR
BG
Expansion Connector
J10
J9
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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