M68360QUADS-040 Hardware User’s Manual
FUNCTIONAL DESCRIPTION
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4.5.3
Spurious Interrupt Monitor
In EC040 mode, the QUICC monitors for spurious interrupt cycles performed by the EC040. This support
is limited to those levels supported internally by the QUICC interrupter, i.e., only on those levels used by
the CPM and the SIM60. If such a condition occurs, the QUICC terminates the cycle with TEA~.
4.5.4
software Watch-Dog
The software watch-dog on the M68360QUADS-040 may be programmed to generate a system reset
when an application software is stuck in an endless loop. The software watch dog is disabled after reset
and it may be enabled if the users want it enabled.
4.5.5
Periodic Interval Timer - PIT
If desired, the QUICC’s PIT may be used to generate periodic interrupt in favor of real-time kernel. The PIT
is disabled after reset.
4.6
Clock Generator
There are two main clocks available on the M68360QUADS-040:
1.
25Mhz system clock, which supplies BCLK for the EC040 and EXTAL clock input for the
QUICC. This clock is supplied via four buffers to the different board area.
2.
50Mhz clock, which supplies the PCLK for the EC040 and is generated using the QUICC’s
PLL via CLKO2. During reset, CLKO2 reflects the state of the EXTAL input and becomes
2 X EXTAL after the QUICC’s PLL is locked.
The 25Mhz clock is generated by an external crystal oscillator (U37) which is divided by 2 to yield a 50%
duty cycle (U39) which is buffered (U38) and distributed to all board consumers.
4.7
Flash PROM
The Flash PROM on the M68360QUADS-040 is constructed of four Am29F010-12 devices providing a
total of 512 KBytes. The Am29F010 is a 5 V programmable, with 8 - sectors’ protection capability, 120 nsec
access time, 128 KByte device, accessed with 3 wait-states @ 25 Mhz system clock. An option is made to
use bigger Flash PROMs up to the Am29F040. The Flash PROM is used to store the resident debugger
and other necessary drivers, which reside in 4 protected sectors. The rest of the sectors are available for
on-board user programming. The Flash PROM is selected using the Global CS (CS0) of the slave QUICC.
To program the Flash PROM, the program (and / or data) should be downloaded to the DRAM (or BSRAM)
and then programmed into the Flash Prom by a dedicated debugger command. If a dedicated
programming routine is to be used it is important to remember that the Flash Prom can NOT be accessed
normally during the programming process. Therefore, the programming routine should reside in another
memory.
4.8
Bursting SRAM
The bursting sram on the M68360QUADS-040 is constructed of two
1
banks, each containing 4
MCM62940AFN12 32K X 9SRAM chips. This RAM provides fast access times for the EC040: 3,1,1,1 clock
cycles for burst access and 3 clock cycles for normal access.
If desired, the volume of the BSRAM may be doubled, this, by soldering identical memory components to
the empty locations designated by U27, U28, U29 & U30.
1. One populated and the other optional
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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