iv
Motorola
2.6
HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7
SERIAL HOST INTERFACE (SHI) . . . . . . . . . . . . . . . . . . . 2-13
2.8
SERIAL AUDIO INTERFACE (SAI) . . . . . . . . . . . . . . . . . . 2-16
2.8.1
SAI Receive Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.8.2
SAI Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.9
GENERAL PURPOSE INPUT/OUTPUT (GPIO) . . . . . . . . 2-18
2.10
DIGITAL AUDIO INTERFACE (DAX) . . . . . . . . . . . . . . . . . 2-18
2.11
ONCE PORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
3.1
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2
DSP56012 DATA AND PROGRAM MEMORY. . . . . . . . . . . 3-3
3.2.1
X and Y Data ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.2
Bootstrap ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3
DSP56012 DATA AND PROGRAM MEMORY MAPS . . . . . 3-4
3.3.1
Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.2
Dynamic Switch of Memory Configurations . . . . . . . . . . . 3-8
3.3.3
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.4
OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . 3-12
3.4.1
DSP Operating Mode (MC, MB, MA)—Bits 4, 1, and 0 . 3-12
3.4.2
Program RAM Enable A and Program RAM Enable B (PEA and
PEB)—Bits 2 and 33-12
3.4.3
Stop Delay (SD)—Bit 6. . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.5
OPERATING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.6
INTERRUPT PRIORITY REGISTER . . . . . . . . . . . . . . . . . 3-15
3.7
PHASE LOCK LOOP (PLL) CONFIGURATION . . . . . . . . . 3-19
3.8
OPERATION ON HARDWARE RESET . . . . . . . . . . . . . . . 3-20
4.1
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2
PORT B CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1
Port B Control (PBC) Register . . . . . . . . . . . . . . . . . . . . . 4-6
4.2.2
Port B Data Direction Register (PBDDR) . . . . . . . . . . . . . 4-7
4.2.3
Port B Data (PBD) Register . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3
PROGRAMMING THE GPIO . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.4
HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.4.1
HI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.4.2
HI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.4.3
HI—DSP Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.4.4
Programming Model—DSP Viewpoint . . . . . . . . . . . . . . 4-13
4.4.4.1
HI Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . 4-14
4.4.4.1.1
HCR HI Receive Interrupt Enable (HRIE)—Bit 0 . 4-15
Summary of Contents for DSP56012
Page 12: ...xii Motorola ...
Page 20: ...xx Motorola ...
Page 21: ...MOTOROLA DSP56012 User s Manual 1 1 SECTION 1 OVERVIEW ...
Page 40: ...1 20 DSP56012 User s Manual MOTOROLA Overview DSP56012 Architectural Overview ...
Page 41: ...MOTOROLA DSP56012 User s Manual 2 1 SECTION 2 SIGNAL DESCRIPTIONS ...
Page 61: ...SECTION 3 MEMORY OPERATING MODES AND INTERRUPTS ...
Page 81: ...MOTOROLA DSP56012 User s Manual 4 1 SECTION 4 PARALLEL HOST INTERFACE ...
Page 148: ...4 68 DSP56012 User s Manual MOTOROLA Parallel Host Interface Host Interface HI ...
Page 149: ...MOTOROLA DSP56012 User s Manual 5 1 SECTION 5 SERIAL HOST INTERFACE ...
Page 179: ...MOTOROLA DSP56012 User s Manual 6 1 SECTION 6 SERIAL AUDIO INTERFACE ...
Page 205: ...MOTOROLA DSP56012 User s Manual 7 1 SECTION 7 GPIO ...
Page 210: ...7 6 DSP56012 User s Manual MOTOROLA GPIO GPIO Register GPIOR ...
Page 211: ...MOTOROLA DSP56012 User s Manual 8 1 SECTION 8 DIGITAL AUDIO TRANSMITTER ...
Page 226: ...8 16 DSP56012 User s Manual MOTOROLA Digital Audio Transmitter DAX Programming Considerations ...
Page 233: ...MOTOROLA DSP56012 User s Manual B 1 APPENDIX B PROGRAMMING REFERENCE ...