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Parallel Host Interface

Host Interface (HI)

MOTOROLA

DSP56012 User’s Manual

4-37

4.4.7

Servicing the HI

The HI can be serviced by using one of the following protocols:

• Polling

• Interrupts, which can be either:

– non-DMA

– DMA

From the host processor viewpoint, the service consists of making a data transfer,
since this is the only way to reset the appropriate status bits.

4.4.7.1

HI—Host Processor Data Transfer

The HI looks like Static RAM to the host processor. Accordingly, in order to transfer
data with the HI, the host processor:

1. asserts the Host Address (HOA[2:0]) to select the register to be read or written;

2. asserts HR/W to select the HI for the current access, and

Figure 4-14 Host Processor Transfer Timing

HOA0–HOA2

H[7:0]

DSP56012

HOA0–HOA2

H[7:0]

HOREQ

HACK

Write

Read

Data

Latched

In Host

AA0322.11

HEN

HR/W

HEN

HR/W

Summary of Contents for DSP56012

Page 1: ...P56012UM D Rev 0 Published 11 98 DSP56012 24 Bit Digital Signal Processor User s Manual Motorola Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin TX 78735 8598 ...

Page 2: ...ver time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support life...

Page 3: ... 2 7 On Chip Emulation OnCE Port 1 13 1 3 3 Memories 1 13 1 3 3 1 Program Memory 1 13 1 3 3 2 X Data Memory 1 15 1 3 3 3 Y Data Memory 1 15 1 3 3 4 On Chip Memory Configuration Bits 1 15 1 3 3 5 Memory Configuration Bits 1 16 1 3 3 6 External Memory 1 16 1 3 3 7 Bootstrap ROM 1 16 1 3 3 8 Reserved Memory Spaces 1 16 1 3 4 Input Output 1 16 1 3 4 1 Parallel Host Interface HI 1 18 1 3 4 2 Serial Hos...

Page 4: ...E REGISTER OMR 3 12 3 4 1 DSP Operating Mode MC MB MA Bits 4 1 and 0 3 12 3 4 2 Program RAM Enable A and Program RAM Enable B PEA and PEB Bits 2 and 33 12 3 4 3 Stop Delay SD Bit 6 3 12 3 5 OPERATING MODES 3 13 3 6 INTERRUPT PRIORITY REGISTER 3 15 3 7 PHASE LOCK LOOP PLL CONFIGURATION 3 19 3 8 OPERATION ON HARDWARE RESET 3 20 4 1 INTRODUCTION 4 3 4 2 PORT B CONFIGURATION 4 3 4 2 1 Port B Control P...

Page 5: ...terrupts 4 20 4 4 4 7 HI Usage Considerations DSP Side 4 21 4 4 5 HI Host Processor Viewpoint 4 21 4 4 5 1 Programming Model Host Processor Viewpoint 4 21 4 4 5 2 Host Command 4 22 4 4 5 3 Interrupt Control Register ICR 4 24 4 4 5 3 1 ICR Receive Request Enable RREQ Bit 0 4 24 4 4 5 3 2 ICR Transmit Request Enable TREQ Bit 1 4 24 4 4 5 3 3 ICR Reserved Bit 2 4 25 4 4 5 3 4 ICR HI Flag 0 HF0 Bit 3 ...

Page 6: ...2 Host Interrupts using Host Request HOREQ 4 38 4 4 7 3 Polling 4 38 4 4 7 4 Servicing Non DMA Interrupts 4 39 4 4 7 5 Servicing DMA Interrupts 4 41 4 4 8 Host Interface Application Examples 4 42 4 4 8 1 HI Initialization 4 42 4 4 8 2 Polling Interrupt Controlled Data Transfer 4 45 4 4 8 2 1 Host to DSP Data Transfer 4 49 4 4 8 2 2 Host to DSP Command Vector 4 51 4 4 8 2 3 Host to DSP Bootstrap Lo...

Page 7: ...5 3 HCKR Divider Modulus Select HDM 5 0 Bits 8 3 5 12 5 4 5 4 HCKR Reserved Bits Bits 23 14 11 9 5 12 5 4 5 5 HCKR Filter Mode HFM 1 0 Bits 13 12 5 12 5 4 6 SHI Control Status Register HCSR DSP Side 5 13 5 4 6 1 HCSR Host Enable HEN Bit 0 5 13 5 4 6 1 1 SHI Individual Reset 5 13 5 4 6 2 HCSR I2 C SPI Selection HI2C Bit 1 5 13 5 4 6 3 HCSR Serial Host Interface Mode HM 1 0 Bits 3 25 14 5 4 6 4 HCSR...

Page 8: ...AL AUDIO INTERFACE INTERNAL ARCHITECTURE 6 4 6 2 1 Baud Rate Generator 6 4 6 2 2 Receive Section Overview 6 5 6 2 3 SAI Transmit Section Overview 6 6 6 3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL 6 8 6 3 1 Baud Rate Control Register BRC 6 9 6 3 1 1 Prescale Modulus select PM 7 0 Bits 7 0 6 10 6 3 1 2 Prescaler Range PSR Bit 8 6 10 6 3 1 3 BRC Reserved Bits Bits 15 9 6 10 6 3 2 Receiver Control Stat...

Page 9: ... 8 TCS Transmitter Clock Polarity TCKP Bit 8 6 19 6 3 4 9 TCS Transmitter Relative Timing TREL Bit 9 6 20 6 3 4 10 TCS Transmitter Data Word Expansion TDWE Bit 106 20 6 3 4 11 TCS Transmitter Interrupt Enable TXIE Bit 11 6 21 6 3 4 12 TCS Transmitter Interrupt Location TXIL Bit 12 6 22 6 3 4 13 TCS Reserved Bit Bit 13 6 22 6 3 4 14 TCS Transmitter Left Data Empty TLDE Bit 14 6 22 6 3 4 15 TCS Tran...

Page 10: ... DAX Channel B User Data XUB Bit 14 8 10 8 5 4 11 DAX Channel B Channel Status XCB Bit 15 8 10 8 5 5 DAX Status Register XSTR 8 10 8 5 5 1 DAX Audio Data Register Empty XADE Bit 0 8 10 8 5 5 2 XSTR Reserved Bits Bits 1 5 23 8 10 8 5 5 3 DAX Transmit Underrun Error Flag XAUR Bit 2 8 10 8 5 5 4 DAX Block Transfer Flag XBLK Bit 3 8 11 8 5 5 5 DAX Transmit In Progress XTIP Bit 4 8 11 8 5 6 DAX Non Aud...

Page 11: ...Motorola xi B 1 INTRODUCTION B 3 B 2 PERIPHERAL ADDRESSES B 3 B 3 INTERRUPT ADDRESSES B 3 B 4 INTERRUPT PRIORITIES B 3 B 5 INSTRUCTION SET SUMMARY B 3 B 6 PROGRAMMING SHEETS B 3 ...

Page 12: ...xii Motorola ...

Page 13: ...FF 3 16 Figure 3 7 PLL Configuration 3 20 Figure 4 1 Port B Interface 4 3 Figure 4 2 Parallel Port B Registers 4 4 Figure 4 3 Port B GPIO Signals and Registers 4 5 Figure 4 4 Port B I O Pin Control Logic 4 6 Figure 4 5 Instructions to Write Read Parallel Data with Port B 4 8 Figure 4 6 I O Port B Configuration 4 9 Figure 4 7 HI Block Diagram 4 12 Figure 4 8 HI Programming Model DSP Viewpoint 4 14 ...

Page 14: ...Host Side Polling Mode 4 46 Figure 4 23 HI Configuration Host Side 4 46 Figure 4 24 HI Initialization Host Side DMA Mode 4 47 Figure 4 25 Bits Used for Host to DSP Transfer 4 48 Figure 4 26 Data Transfer from Host to DSP 4 50 Figure 4 27 Host Command 4 52 Figure 4 28 Receive Data from Host Main Program 4 53 Figure 4 29 Receive Data from Host Interrupt Routine 4 53 Figure 4 30 Transmit Receive Byte...

Page 15: ... the I2 C Bus 5 21 Figure 5 10 I2 C Bus Protocol For Host Write Cycle 5 22 Figure 5 11 I2C Bus Protocol For Host Read Cycle 5 22 Figure 6 1 SAI Baud Rate Generator Block Diagram 6 4 Figure 6 2 SAI Receive Section Block Diagram 6 5 Figure 6 3 SAI Transmit Section Block Diagram 6 7 Figure 6 4 SAI Registers 6 8 Figure 6 5 Receiver Data Shift Direction RDIR Programming 6 12 Figure 6 6 Receiver Left Ri...

Page 16: ...6 20 Figure 6 14 Transmitter Data Word Expansion TDWE Programming 6 21 Figure 7 1 GPIO Control Data Register 7 3 Figure 7 2 GPIO Circuit Diagram 7 5 Figure 8 1 Digital Audio Transmitter DAX Block Diagram 8 4 Figure 8 2 DAX Programming Mode 8 7 Figure 8 3 DAX Relative Timing 8 11 Figure 8 4 Preamble sequence 8 13 Figure 8 5 Clock Multiplexer Diagram 8 13 Figure B 1 On chip Peripheral Memory Map B 4...

Page 17: ... 6 Table 2 4 Phase Lock Loop Signals 2 7 Table 2 5 Interrupt and Mode Control 2 8 Table 2 6 Host Interface 2 10 Table 2 7 Serial Host Interface SHI Signals 2 13 Table 2 8 Serial Audio Interface SAI Receive Signals 2 16 Table 2 9 Serial Audio Interface SAI Transmit Signals 2 17 Table 2 10 General Purpose I O GPIO Signals 2 18 Table 2 11 Digital Audio Interface DAX Signals 2 18 Table 2 12 On Chip Em...

Page 18: ...ble 5 3 SHI Noise Reduction Filter Mode 5 12 Table 5 4 SHI Data Size 5 14 Table 5 5 HREQ Function In SHI Slave Modes 5 15 Table 5 6 HCSR Receive Interrupt Enable Bits 5 17 Table 6 1 SAI Interrupt Vector Locations 6 9 Table 6 2 SAI Internal Interrupt Priorities 6 9 Table 6 3 Receiver Word Length Control 6 11 Table 6 4 Transmitter Word Length 6 18 Table 7 1 GPIO Pin Configuration 7 4 Table 8 1 DAX I...

Page 19: ...Motorola xix Table B 2 Interrupt Priorities Within an IPL B 6 Table B 3 Instruction Set Summary Sheet 1 of 7 B 8 ...

Page 20: ...xx Motorola ...

Page 21: ...MOTOROLA DSP56012 User s Manual 1 1 SECTION 1 OVERVIEW ...

Page 22: ... 1 INTRODUCTION 1 3 1 1 1 Manual Organization 1 4 1 1 2 Manual Conventions 1 5 1 2 DSP56012 FEATURES 1 6 1 3 DSP56012 ARCHITECTURAL OVERVIEW 1 8 1 3 1 Peripheral Modules 1 10 1 3 2 DSP Core Processor 1 10 1 3 3 Memories 1 13 1 3 4 Input Output 1 16 ...

Page 23: ...p audio decoding Flexible peripheral modules and interface software allow simple connection to a wide variety of video and audio system decoders The memory configuration and peripherals differentiate this DSP from the other 56000 family members The DSP56012 also provides the following on chip peripherals to support its target applications Parallel Host Interface HI a byte wide parallel port with D...

Page 24: ...on 5 Serial Host Interface describes the operation registers and control of the Serial Host Interface SHI Section 6 Serial Audio Interface describes the operation of the Serial Audio Interface SAI its registers and its controls Section 7 Digital Audio Transmitter describes the Digital Audio Transmitter DAX functionality architecture registers and programming considerations Section 8 Serial Audio I...

Page 25: ...ed as cleared its value is 0 Hex hexadecimal values are indicated with a dollar sign preceding the hex value as in FFFB is the X memory address for the Interrupt Priority Register IPR Code examples are displayed in a monospaced font as shown in Example 1 1 Pins or signals listed in code examples that are asserted low have a tilde in front of their names The word assert means that a high true activ...

Page 26: ...e Fractional and integer arithmetic with support for multi precision arithmetic Hardware support for block floating point Fast Fourier Transforms FFT Hardware nested DO loops Zero overhead fast interrupts 2 instruction cycles Table 1 1 High True Low True Signal Conventions Signal Symbol Logic State Signal State Voltage PIN1 True Asserted VCC 3 PIN1 False Deasserted Ground2 PIN1 True Asserted Groun...

Page 27: ... bit on chip Program RAM and 32 24 bit bootstrap ROM As much as 2304 24 bits of X and Y data RAM can be switched to Program RAM giving a total of 2560 24 bits of Program RAM Table 1 2 lists the memory configurations of the DSP56012 Peripheral and Support Circuits SAI includes Two receivers and three transmitters Master or slave capability I2S Sony and Matshushita audio protocol implementations 1 T...

Page 28: ...ock Power saving Wait and Stop modes Fully static HCMOS design for operating frequencies from 81 MHz down to DC 100 pin plastic Thin Quad Flat Pack TQFP surface mount package 5 V power supply 1 3 DSP56012 ARCHITECTURAL OVERVIEW The DSP56012 is a member of the 24 bit DSP56000 family The DSP is composed of the 24 bit DSP56000 core memory and a set of peripheral modules as shown in Figure 1 1 The 24 ...

Page 29: ... audio applications since its arithmetic operations are executed on 24 bit or 48 bit data words This is a significant advantage for audio over 16 bit and 32 bit architectures 16 bit DSP architectures have insufficient precision for CD quality sound and while 32 bit DSP architectures possess the necessary precision with extra silicon and cost overhead they are not suitable for high volume cost driv...

Page 30: ...e that allows the DSP56012 to communicate using a wide range of standard serial data formats used by audio manufacturers at bit rates up to one third the DSP core clock rate e g 27 MHz for an 81 MHz clock There are three synchronized data transmission lines and two synchronized data reception lines all of which are double buffered General Purpose Input Output GPIO The GPIO has eight dedicated sign...

Page 31: ... YDB The data shifters are capable of shifting data one bit to the left or to the right as well as passing the data unshifted Each data shifter has a 24 bit output with overflow indication The data shifters are controlled by scaling mode bits These shifters permit no overhead dynamic scaling of fixed point data by simply programming the scaling mode bits This permits block floating point algorithm...

Page 32: ...h as I O transfers to internal peripherals occur over the GDB Instruction word pre fetches take place over the PDB in parallel with data transfers Transfers between buses are accomplished through the internal bus switch 1 3 2 5 Address Buses Addresses are specified for internal X data memory and Y data memory using two unidirectional 16 bit buses the X Address Bus XAB and the Y Address Bus YAB pro...

Page 33: ...trol Logic usually the Program Counter over the Program Address Bus PAB Program memory may be written using MOVEM instructions The interrupt vectors are located in the bottom 128 locations of program memory Table 1 3 lists the interrupt vector addresses and indicates the Interrupt Priority Level IPL of each interrupt source Program RAM has many advantages It provides a means to develop code effici...

Page 34: ...run Error P 002C 0 2 SHI Bus Error P 002E Reserved P 0030 0 2 Host Receive Data P 0032 0 2 Host Transmit Data P 0034 0 2 Host Command default P 0036 Reserved available for Host Command see p B 5 B 6 P 003C Reserved available for Host Command see p B 5 B 6 P 003E 3 Illegal Instruction P 0040 0 2 SAI Left Channel Transmitter if TXIL 1 P 0042 0 2 SAI Right Channel Transmitter if TXIL 1 P 0044 0 2 SAI...

Page 35: ... see Table 1 4 Section 3 provides detailed information about memory configuration P 0050 0 2 DAX Transmit Underrun Error P 0052 0 2 DAX Block Transferred P 0054 Reserved available for Host Command see p B 5 B 6 P 0056 0 2 DAX Transmit Register Empty P 0058 Reserved available for Host Command see p B 5 B 6 Reserved available for Host Command see p B 5 B 6 P 007E Reserved available for Host Command ...

Page 36: ...uture versions or variants of this DSP Write operations to the reserved range are ignored Read operations from addresses in the reserved range with values greater than or equal to 2E00 in X memory space and 2800 in Y memory space and values from the reserved area of program memory space return the value 000005 which is the opcode for the ILLEGAL instruction and causes an illegal instruction interr...

Page 37: ...ter HSAR X FFF1 SHI Host Control Status Register HCSR X FFF0 SHI Host Clock Control Register HCKR X FFEF Reserved X FFEE Port B Data Register PBD X FFED Port B Data Direction Register PBDDR X FFEC Port B Control Register PBC X FFEB Host Receive Transmit Register HORX HOTX X FFEA Reserved X FFE9 Host Status Register HSR X FFE8 Host Control Register HCR X FFE7 SAI TX2 Data RegisteR TX2 X FFE6 SAI TX...

Page 38: ...face SHI provides a serial path for communication and program coefficient data transfers between the DSP and an external host processor or other serial peripheral devices This interface can connect directly to one of two well known and widely used synchronous serial buses the Serial Peripheral Interface SPI bus defined by Motorola and the Inter Integrated circuit Control I2 C bus defined by Philip...

Page 39: ...r consists of two receivers and a single receive controller This enables simultaneous data reception from up to two stereo audio devices The transmit and receive sections are fully asynchronous and may transmit and receive at different rates see Section 6 Serial Audio Interface 1 3 4 4 General Purpose I O The General Purpose Input Output GPIO pins are used for control and handshake functions betwe...

Page 40: ...1 20 DSP56012 User s Manual MOTOROLA Overview DSP56012 Architectural Overview ...

Page 41: ...MOTOROLA DSP56012 User s Manual 2 1 SECTION 2 SIGNAL DESCRIPTIONS ...

Page 42: ...POWER 2 5 2 3 GROUND 2 6 2 4 PHASE LOCK LOOP PLL 2 7 2 5 INTERRUPT AND MODE CONTROL 2 8 2 6 HOST INTERFACE HI 2 10 2 7 SERIAL HOST INTERFACE SHI 2 13 2 8 SERIAL AUDIO INTERFACE SAI 2 16 2 9 GENERAL PURPOSE INPUT OUTPUT GPIO 2 18 2 10 DIGITAL AUDIO INTERFACE DAX 2 18 2 11 OnCE PORT 2 19 ...

Page 43: ...ge 2 4 Table 2 1 DSP56012 Functional Signal Groupings Functional Group Number of Signals Detailed Description Power VCC 13 Table 2 2 Ground GND 17 Table 2 3 PLL 4 Table 2 4 Interrupt and Mode Control 4 Table 2 5 Host Interface HI Port B 15 Table 2 6 Serial Host Interface SHI 5 Table 2 7 Serial Audio Interface SAI 9 Table 2 8 Table 2 9 General Purpose Input Output GPIO 8 Table 2 10 Digital Audio Tr...

Page 44: ...erial Audio Interface SAI Rec0 Rec1 Tran0 Tran1 Tran2 1 2 3 Grounds PLL Internal Logic A D HI SHI GNDP GNDQ GNDA GNDD GNDH GNDS 4 3 2 3 Interrupt Mode Control MODA IRQA MODB IRQB MODC NMI RESET Host Interface HI Port H0 H7 HOA0 HOA1 HOA2 HR W HEN HOREQ HACK WSR SCKR SDI0 SDI1 WST SCKT SDO0 SDO1 SDO2 ADO ACI 8 2 4 Serial Host Interface SHI MOSI HA0 SS HA2 MISO SDA SCK SCL HREQ Port B GPIO PB0 PB7 P...

Page 45: ...citors VCCA A Power VCCA is an isolated power for sections of the internal chip logic This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors VCCD D Power VCCD is an isolated power for sections of the internal chip logic This input must be tied externally to all other chip power inputs The user must provide adequate external d...

Page 46: ...ground for sections of the internal logic This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors GNDD D Ground GNDD is an isolated ground for sections of the internal logic This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors GNDH...

Page 47: ... state During hardware reset the PLOCK state is determined by PINIT and the current PLL lock condition PCAP Input Input PLL Capacitor PCAP is an input connecting an off chip capacitor to the PLL filter Connect one capacitor terminal to PCAP and the other terminal to VCCP If the PLL is not used PCAP may be tied to VCC GND or left floating PINIT Input Input PLL Initial During assertion of RESET the ...

Page 48: ...xternal interrupt request that indicates that an external device is requesting service It may be programmed to be level sensitive or negative edge sensitive If the processor is in the Stop state and IRQA is asserted the processor will exit the Stop state MODB IRQB Input Input Mode Select B External Interrupt Request B This input has two functions 1 to select the initial chip operating mode and 2 a...

Page 49: ...fter reset the chip operating mode can be changed by software The NMI input is an external interrupt request that indicates that an external device is requesting service It may be programmed to be level sensitive or negative edge sensitive RESET Input Input Reset This input is a direct hardware reset on the processor When RESET is asserted low the DSP is initialized and placed in the Reset state A...

Page 50: ...t the H0 H7signals are tri stated as long as HEN is deasserted The signals are inputs unless HR W is high and HEN is asserted in which case H0 H7 become outputs allowing the host processor to read the DSP56012 data H0 H7 become outputs when HACK is asserted during HOREQ assertion Port B GPIO 0 7 PB0 PB7 These signals are General Purpose I O signals PB0 PB7 when the Host Interface is not selected A...

Page 51: ... and the host processor may read DSP56011 data When HEN is asserted and HR W is low H0 H7 become inputs Host data is latched inside the DSP on the rising edge of HEN Normally a chip select signal derived from host address decoding and an enable strobe are used to generate HEN Port B GPIO 12 PB12 This signal is a General Purpose I O signal PB12 when the Host Interface is not being used After reset ...

Page 52: ...ransfers and it receives a host interrupt acknowledge compatible with MC68000 family processors Note HACK should always be pulled high when it is not in use Port B GPIO 14 PB14 This signal is a General Purpose I O signal PB14 when the Host Interface is not selected After reset the default state for this signal is GPIO input Table 2 6 Host Interface Continued Signal Name Type State During Reset Sig...

Page 53: ...l from the external master synchronizes the data transfer The SCK signal is ignored by the SPI if it is defined as a slave and the Slave Select SS signal is not asserted In both the master and slave SPI devices data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable Edge polarity is determined by the SPI transfer protocol SCL carries the clock for I2 ...

Page 54: ...ange during the time SCL is high in the case of start and stop events A high to low transition of the SDA line while SCL is high is an unique situation which is defined as the start event A low to high transition of SDA while SCL is high is an unique situation which is defined as the stop event An external pull up resistor is not required MOSI HA0 Input or Output Tri stated SPI Master Out Slave In...

Page 55: ...d during hardware software or personal reset no need for external pull up in this state HREQ Input or Output Tri stated Host Request This signal is an active low Schmitt trigger input when configured for the Master mode but an active low output when configured for the Slave mode When configured for the Slave mode HREQ is asserted to indicate that the SHI is ready for the next data word transfer an...

Page 56: ...ce during hardware or software reset while receiver 1 is disabled R1EN 0 or while the chip is in the Stop state No external pull up resistor is required SCKR Input or Output Tri stated Receive Serial Clock SCKR is an output if the receiver section is programmed as a master and a Schmitt trigger input if programmed as a slave SCKR is high impedance if all receivers are disabled personal reset and d...

Page 57: ...e reset or when the chip is in the Stop state SCKT Input or Output Tri stated Transmit Serial Clock This signal provides the clock for the Serial Audio Interface SAI The SCKT signal can be an output if the transmit section is programmed as a master or a Schmitt trigger input if the transmit section is programmed as a slave When the SCKT is an output it provides an internally generated SAI transmit...

Page 58: ...terface DAX Signals Signal Name Type State During Reset Signal Description ADO Output Output driven high Digital Audio Data Output This signal is an audio and non audio output in the form of AES EBU CP340 and IEC958 data in a biphase mark format The signal is driven high when the DAX is disabled and during hardware or software reset ACI Input Tri stated Audio Clock Input This is the DAX clock inpu...

Page 59: ... input the signal is tri stated Note If the OnCE interface is in use an external pull down resistor should be attached to this pin If the OnCE interface is not in use the resistor is not required DSCK OS1 Input O utput Low Output Debug Serial Clock Chip Status 1 The DSCK OS1 signal supplies the serial clock to the OnCE when it is an input The serial clock provides pulses required to shift data int...

Page 60: ...n after the data is written another acknowledge pulse will be provided DR Input Input Debug Request The debug request input DR allows the user to enter the Debug mode of operation from the external command controller When DR is asserted it causes the DSP to finish the current instruction being executed save the instruction pipeline information enter the Debug mode and wait for commands to be enter...

Page 61: ...SECTION 3 MEMORY OPERATING MODES AND INTERRUPTS ...

Page 62: ...Y MAPS 3 4 3 3 1 Reserved Memory Spaces 3 5 3 3 2 Dynamic Switch of Memory Configurations 3 7 3 3 3 Internal I O Memory Map 3 9 3 4 OPERATING MODE REGISTER OMR 3 11 3 4 1 DSP Operating Mode MC MB MA Bits 4 1 and 0 3 11 3 4 2 Program RAM Enable A PEA Bit 2 3 11 3 4 3 Program RAM Enable B PEB Bit 3 3 11 3 4 4 Stop Delay SD Bit 6 3 12 3 5 OPERATING MODES 3 12 3 6 INTERRUPT PRIORITY REGISTER 3 14 3 7 ...

Page 63: ...his section also includes details of the interrupt vectors and priorities and describes the effect of a hardware reset on the PLL Multiplication Factor MF 3 2 DSP56012 DATA AND PROGRAM MEMORY The memory in the DSP56012 can be mapped into four different configurations according to the PEA and PEB bits of the OMR register The internal data and program memory configurations are shown in Table 3 1 Not...

Page 64: ...ed by the mode bits The mode selected by the MOD pin MOD bit values can select a bypass mode Mode 4 that causes the DSP to use the on chip Program ROM or one of three bootstrap modes Modes 1 5 and 7 When in one of the three bootstrap modes the first 256 words of Program RAM are disabled for read but accessible for write and the bootstrap routine loads up to 256 words into the reserved RAM space Th...

Page 65: ...sed by the user They are reserved to retain compatibility with future enhanced or derivative versions of this device Write operations to the reserved range are ignored Read operations from addresses in the reserved range return the value 000005 which is the opcode for the ILLEGAL instruction If an instruction fetch is attempted from an address in the reserved area the value returned is 000005 ILLE...

Page 66: ...3 6 DSP56012 User s Manual MOTOROLA Memory Operating Modes and Interrupts DSP56012 Data and Program Memory Maps Figure 3 2 Memory Maps for PEA 1 PEB 0 ...

Page 67: ...Memory Operating Modes and Interrupts DSP56012 Data and Program Memory Maps MOTOROLA DSP56012 User s Manual 3 7 Figure 3 3 Memory Maps for PEA 0 PEB 1 ...

Page 68: ...amically switched from one configuration to another by changing the PEA and PEB bits in the OMR The address ranges that are directly affected by the switch operation are P 0200 0AFF X 0A00 0FFF and Y 0E00 10FF see Figure 3 1 Figure 3 2 Figure 3 3 and Figure 3 4 The memory switch can be accomplished provided that the affected address ranges are not being accessed during the instruction cycle in whi...

Page 69: ...led at least four instruction cycles before switching due to pipeline latency of the interrupt processing Special attention should be given when running a memory switch routine using the OnCE port Running the switch routine in Trace mode for example can cause the switch to complete after the PEA PEB bit changes while the DSP is in Debug mode As a result subsequent instructions might be fetched acc...

Page 70: ...followed by an NOP as a delay for remapping and then followed by a JMP long or another NOP and JMP short instead 3 3 3 Internal I O Memory Map The DSP56012 on chip peripheral modules have their registers mapped to the addresses in the internal I O memory range as shown in Table 3 2 Note Location X FFFE is the Bus Control Register BCR for the DSP56000 core Although labelled Reserved on the DSP56012...

Page 71: ...gister PBC X FFEB Host Receive Transmit Register HORX HOTX X FFEA Reserved X FFE9 Host Status Register HSR X FFE8 Host Control Register HCR X FFE7 SAI TX2 Data Register TX2 X FFE6 SAI TX1 Data Register TX1 X FFE5 SAI TX0 Data Register TX0 X FFE4 SAI TX Control Status Register TCS X FFE3 SAI RX1 Data Register RX1 X FFE2 SAI RX0 Data Register RX0 X FFE1 SAI RX Control Status Register RCS X FFE0 SAI ...

Page 72: ... Enable B PEB bits are used to alter the memory configuration on the DSP56012 Refer to Table 3 1 on page 3 3 for a summary of the memory configurations The internal memory maps as selected by the PEA and PEB bits are shown in Figure 3 1 through Figure 3 4 PEA and PEB are cleared by hardware reset 3 4 3 Stop Delay SD Bit 6 When leaving the Stop state the Stop Delay SD bit is interrogated If the SD ...

Page 73: ...56002 Mode 0 Note It is not possible to reach operating Mode 0 during hardware reset Any attempt to start up in Mode 0 defaults to Mode 1 Mode 1 In this mode the bootstrap ROM is enabled and the bootstrap program is executed after hardware reset The internal Program RAM is loaded with up to 256 words from the parallel Host Interface Mode 2 Reserved Mode 3 Reserved Note It is not possible to reach ...

Page 74: ... words from the Serial Host Interface SHI The SHI operates in the SPI Slave mode with 24 bit word width Mode 6 Reserved Note It is not possible to reach operating Mode 6 during hardware reset Any attempt to start up in Mode 6 defaults to Mode 1 Mode 7 In this mode the bootstrap ROM is enabled and the bootstrap program is executed after hardware reset The internal Program RAM is loaded with 256 oor...

Page 75: ...ty levels IPL 0 1 or 2 IPLs are set by writing to the IPR The IPR configuration is shown in Figure 3 6 Bits 5 0 of the IPR are used by the DSP56000 core for two of the external interrupt request inputs IRQA IAL 2 0 and IRQB IBL 2 0 assuming the same IPL IRQA has higher a priority than IRQB Bits 9 6 and 23 18 are reserved for future use Bits 17 10 are available for determining IPLs for each periphe...

Page 76: ...struction NMI Stack Error Trace SWI Levels 0 1 2 Maskable Highest IRQA IRQB SAI Receiver Exception SAI Transmitter Exception SAI Left Channel Receiver SAI Left Channel Transmitter IAL1 IAL0 IAL2 IBL0 IBL1 IBL2 SAL0 SAL1 0 11 10 9 8 7 6 5 4 3 2 1 Reserved read as 0 and should be written with 0 for future compatibility SHL1 SHL0 HPL0 HPL1 12 23 22 21 20 19 18 17 16 15 14 13 IRQA Mode IRQB Mode Reser...

Page 77: ... Interrupt HOST Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred Lowest DAX Transmit Register Empty Table 3 5 Interrupt Vectors Address Interrupt Source P 0000 Hardware RESET P 0002 Stack Error P 0004 Trace P 0006 SWI P 0008 IRQA P 000A IRQB P 000C Reserved P 000E Reserved P 0010 SAI Left Channel Transmitter if TXIL 0 P 0012 SAI Right Channel Transmitter if TXIL 0 P 0014 S...

Page 78: ...run Error P 002C SHI Bus Error P 002E Reserved P 0030 Host Receive Data P 0032 Host Transmit Data P 0034 Host Command Default P 0036 Reserved P 003C Reserved P 003E Illegal Instruction P 0040 SAI Left Channel Transmitter if TXIL 1 P 0042 SAI Right Channel Transmitter if TXIL 1 P 0044 SAI Transmitter Exception if TXIL 1 P 0046 SAI Left Channel Receiver if RXIL 1 P 0048 SAI Right Channel Receiver if...

Page 79: ...k Source Bit CSRC is set and the PLL VCO frequency is divided by the Low Power Divider LPD and then used as the internal DSP clock if the CSRC bit is cleared The DSP56012 PLL Multiplication Factor is set to 3 during hardware reset which means that the Multiplication Factor bits MF1 1 0 in the PCTL are set to 002 The PLL may be disabled PEN 0 upon reset by pulling the PINIT pin low The DSP will sub...

Page 80: ... Double Precision Multiply mode and condition code bits and sets the interrupt mask bits of the Status Register SR and clears the Stop Delay SD bit and the Program RAM Enable PEA and PEB bits in the OMR The DSP remains in the Reset state until the RESET pin is deasserted When the processor leaves the Reset state it loads the chip operating mode bits of the OMR from the external mode select pins MO...

Page 81: ...MOTOROLA DSP56012 User s Manual 4 1 SECTION 4 PARALLEL HOST INTERFACE ...

Page 82: ...4 2 DSP56012 User s Manual MOTOROLA Parallel Host Interface 4 1 INTRODUCTION 4 3 4 2 PORT B CONFIGURATION 4 3 4 3 PROGRAMMING THE GPIO 4 8 4 4 HOST INTERFACE HI 4 9 ...

Page 83: ...Port B functionality is controlled by three memory mapped registers see Figure 4 2 on page 4 4 that define the functions associated with fifteen external pins see Figure 4 3 on page 4 5 They are Port B Control register PBC Port B Data Direction Register PBDDR Port B Data register PBD Figure 4 4 on page 4 6 shows an overview of the Port B control logic Note Because reset clears both the PBC and PBD...

Page 84: ...Direction 0 Input Reset Condition 1 Output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BC 1 BC 0 X FFEC Port B Control Register 0 0 0 0 0 0 0 0 BD 14 BD 13 BD 12 BD 11 BD 10 BD 9 BD 8 BD 7 BD 6 BD 5 BD 4 BD 3 BD 2 BD 1 BD 0 23 0 X FFED Port B Data Direction Register 23 0 X FFEE Port B Data Register 0 0 0 0 0 0 0 0 PB 14 PB 13 PB 12 PB 11 PB 10 PB 9 PB 8 PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 23 0...

Page 85: ...B11 PB12 PB13 PB14 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BC0 BC1 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 Enabled by bits in X FFEC Direction Selected by bits in X FFED PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 Input Output Data X FFEE AA0309 11 PBC PBDDR PBD ...

Page 86: ...ammed by writing to the PBC register Writing a 1 to the register defines the pins as the HI port Writing a 2 to the PBC register defines the pins as an HI port without a HACK signal the pin used by HACK in the HI is defined as a GPIO pin PB14 Figure 4 4 Port B I O Pin Control Logic Port Control Register Bit Data Direction Register Bit Pin Function 0 0 Port B Input Pin 0 1 Port B Output Pin 1 X HI ...

Page 87: ...PBD register to be used as a general purpose register If the processor writes to the PBD register the data is latched there and appears on the pin during the following instruction cycle Note If a pin is configured as a host pin the Port B GPIO registers can help in debugging HI operations If the PBDDR bit for a given pin configured as an input i e 0 the PBD register shows the logic level on the pi...

Page 88: ...d for internal and external I O respectively The bit oriented instructions that use I O short addressing BCHG BCLR BSET BTST JCLR JSCLR JSET and JSSET can also address individual bits for faster I O processing The DSP does not have a hardware data strobe to move data out of the GPIO port If a strobe is needed use software to toggle one of the GPIO pins to emulate a strobe signal Figure 4 6 on page...

Page 89: ...f two banks of registers one bank accessible to the host processor and a second bank accessible to the DSP Central Processing Unit CPU see Figure 4 7 on page 4 12 Note Unlike other DSPs in this Motorola family this device uses the SHI for a host control interface and the HI as a high speed parallel data transfer interface Figure 4 6 I O Port B Configuration BC 1 BC 0 15 0 X FFEC Port B Control Reg...

Page 90: ... Write select HOREQ HI Request HACK HI Acknowledge Interface DSP CPU side Mapping three X memory locations Data Word 24 bits Transfer Modes DSP to Host Host to DSP Host Command Handshaking Protocols Software polled Interrupt driven fast or long interrupts Direct Memory Access DMA Instructions Memory mapped registers allow the standard MOVE instruction to be used SpecialMOVEPinstructionprovidesforI...

Page 91: ...h Initialization Dedicated Interrupts Separate interrupt vectors for each interrupt source Special host commands force DSP CPU interrupts under host processor control which are useful for Real time production diagnostics Debugging window for program development Host control protocols and DMA setup 4 4 2 HI Block Diagram Figure 4 7 is a block diagram illustrating the registers in the HI These regis...

Page 92: ...d Memory mapping allows communication with the HI registers to use Figure 4 7 HI Block Diagram DSP CPU Global Data Bus X FFE8 X FFE9 X FFEB X FFEB 24 Receive Byte Registers Transmit Byte Registers Interrupt Control Register Read Write 0 ICR 1 CVR HCR HSR 2 ISR 3 IVR Control Logic HOTX HORX 5 RXH 6 RXM 7 RXL 5 TXH 6 TXM 7 TXL Host Control Register Read Write Host Status Register Read Only Host Tran...

Page 93: ... one for the host processor programmer In most cases the notation used reflects the DSP perspective The host to HI programming model is shown in Figure 4 8 There are three registers the HI Control Register HCR the HI Status Register HSR and a HI data Transmit Receive register HOTX HORX These registers can only be accessed by the DSP56012 they can not be accessed by the host processor The HI to hos...

Page 94: ...s and flags The HCR cannot be accessed by the host processor It occupies the low order byte of the internal data bus the high order Figure 4 8 HI Programming Model DSP Viewpoint X FFE8 DSP CPU Flags Host Flag 3 Host Flag 2 Interrupt Enables Host Receive Host Transmit Host Command Host Control Register HCR Read Write X FFE9 Host Flags Host Flag 1 Host Flag 0 Host Receive Data Full Host Transmit Dat...

Page 95: ...n the HSR is set When HTIE is cleared HTDE interrupts are disabled When HTIE is set a host transmit data interrupt request will occur if HTDE is also set Note Hardware reset and software reset clear the HTIE 4 4 4 1 3 HCR HI Command Interrupt Enable HCIE Bit 2 The HI Command Interrupt Enable HCIE bit is used to enable a vectored DSP interrupt when the HI Command Pending HCP status bit in the HSR i...

Page 96: ...rrogate the HI status and flags bits The HSR can not be directly accessed by the host processor When the HSR is read to the internal data bus the register contents occupy the low order byte of the data bus the high order portion is 0 filled The HSR status bits are described in the following paragraphs 4 4 4 2 1 HSR HI Receive Data Full HRDF Bit 0 The HI Receive Data Full HRDF bit indicates that th...

Page 97: ...o clears HCP Note Hardware reset software reset individual reset and Stop mode clear HCP 4 4 4 2 4 HSR HI Flag 0 HF0 Bit 3 The HI Flag 0 HF0 bit in the HSR indicates the state of Host Flag 0 in the ICR on the host processor side HF0 in HSR can only be changed by the host processor see Figure 4 9 Note Hardware reset software reset individual reset and Stop mode clear HF0 4 4 4 2 5 HSR HI Flag 1 HF1...

Page 98: ...SP Note Hardware reset software reset individual reset and Stop clear the DMA bit 4 4 4 3 HI Receive Data Register HORX The HI Receive data register HORX is used for host to DSP data transfers The HORX register is viewed as a 24 bit read only register by the DSP CPU The HORX register is loaded with 24 bit data from the Transmit data registers TXH TXM TXL on the host processor side when both the ho...

Page 99: ...ansferred as 24 bit data to the Receive byte registers RXH RXM RXL if both the DSP side HTDE bit and host side Receive Data Full RXDF status bits are cleared This transfer operation sets RXDF and HTDE Data should not be written to the HOTX until HTDE is set to prevent the previous data from being overwritten Note Resets do not affect HOTX 4 4 4 5 Register Contents After Reset Table 4 1 shows the r...

Page 100: ...rvice routine The three possible interrupts are 1 receive data register full 2 transmit data register empty and 3 host command The host command can access any interrupt vector in the interrupt vector table although it has a set of vectors reserved for host command use The DSP interrupt service routine must read or write the appropriate HI register clearing HRDF or HTDE for example to clear the int...

Page 101: ...e HI asynchronously by using either polling techniques or interrupt based techniques Separate transmit and receive data registers are double buffered to allow the DSP CPU and host processor to transfer data efficiently at high speed The HI contains a rudimentary DMA controller which makes generating addresses HOA 2 0 for the TX RX registers in the HI unnecessary 4 4 5 1 Programming Model Host Proc...

Page 102: ... host processor and the DSP at the fastest host processor data rate DMA hardware can be used without host processor intervention using the handshake flags to transfer data 4 4 5 2 Host Command One of the most innovative features of the HI is the host command feature With this feature the host processor can issue vectored interrupt requests to the DSP56012 The host can select any one of sixty four ...

Page 103: ...1 24 Bit DMA Mode 1 0 GPIO Bit DMA Mode 1 1 8 Bit DMA Mode Host Vector 17 Status Flags RXL Receive Low Byte TXL Transmit Low Byte Receive Byte Registers RXH RXM RXL Read Only Transmit Byte Registers TXH TXM TXL Write Only 2 Interrupt Status Register ISR Read Only HOREQ 0 0 HF3 0 HF2 0 TRDY 1 TXDE 1 RXDF 0 7 0 31 24 23 0 7 0 7 0 0 7 0 7 8 7 16 15 7 6 5 4 3 Interrupt Vector Register IVR Read Write 7...

Page 104: ...led When RREQ is set the external HOREQ pin will be asserted if RXDF is set In DMA modes RREQ must be set or cleared by software to select the direction of DMA transfers Setting RREQ sets the direction of DMA transfer to be DSP to host and enables the HOREQ pin to request data transfer Note Hardware reset software reset individual reset and Stop clear RREQ 4 4 5 3 2 ICR Transmit Request Enable TRE...

Page 105: ...ld be written with 0 for compatibility with future device revisions 4 4 5 3 4 ICR HI Flag 0 HF0 Bit 3 The HI Flag 0 HF0 bit is used as a general purpose flag for host to DSP communication HF0 can be set or cleared by the host processor and cannot be changed by the DSP HF0 is visible to the DSP as the read only flag HF0 in the HSR see Figure 4 9 on page 4 18 Note Hardware reset software reset indiv...

Page 106: ...CR HI Mode Control HM1 and HM0 Bits 5 and 6 The HI Mode Control 1 HM1 and HI Mode Control 0 HM0 bits select the transfer mode of the HI see Table 4 3 HM1 and HM0 enable the DMA mode of operation or the Interrupt non DMA mode of operation Table 4 3 HI Mode Bit Definition HM1 HM0 Mode 0 0 Interrupt Mode DMA Off 0 1 DMA Mode 24 bit 1 0 DMA Mode 16 bit 1 1 DMA Mode 8 bit Mask HCR X FFE8 Status 0 HF3 H...

Page 107: ... address counter can be initialized with the INIT bit feature After each DMA transfer on the host data bus the address counter is incremented to the next register When the address counter reaches the highest register RXL or TXL the address counter is not incremented but is loaded with the value in HM1 and HM0 This allows 8 16 or 24 bit data to be transferred in a circular fashion and eliminates th...

Page 108: ...counter and clears the channel according to TREQ and RREQ INIT execution is not affected by HM1 and HM0 The internal DMA counter is incremented with each DMA transfer each HACK pulse until it reaches the last data register RXL or TXL When the DMA transfer is completed the counter is loaded with the value of the HM1 and HM0 bits When changing the size of the DMA word changing HM0 and HM1 in the ICR...

Page 109: ... HI Vector HV Bits 0 5 The six HI Vector HV bits select the host command interrupt address to be used by the host command interrupt logic When the host command interrupt is recognized by the DSP interrupt control logic the starting address of the interrupt taken is 2 HV The host can write HC and HV in the same write cycle if desired The host processor can select any of the sixty four possible inte...

Page 110: ...ear HC 4 4 5 6 Interrupt Status Register ISR The Interrupt Status Register ISR is an 8 bit read only status register used by the host processor to interrogate the status and flag bits of the HI The host processor can write to this address without affecting the internal state of the HI This is allows a program to access all of the HI registers by stepping through the HI addresses The ISR can not be...

Page 111: ...s that both the TXH TXM TXL and the HORX registers are empty TRDY TXDE HRDF When TRDY is set the data that the host processor writes to TXH TXM and TXL will be immediately transferred to the DSP CPU side of the HI This has many applications For example if the host processor issues a host command that causes the DSP CPU to read the HORX the host processor can be guaranteed that the data it just tra...

Page 112: ...asserted indicating that the DSP is interrupting the host processor or that a DMA transfer request is occurring The HOREQ interrupt request can originate from either or both of two sources the receive byte registers are full or the transmit byte registers are empty These conditions are indicated by the ISR RXDF and TXDE status bits respectively If the interrupt source has been enabled by the assoc...

Page 113: ...t Low TXL These three registers send data to the high byte middle byte and low byte respectively of the HORX register and are selected by three external host address inputs HOA 2 0 during a host processor write operation Data can be written into the transmit byte registers when the Transmit Data Register Empty TXDE bit is set The host processor can program the TREQ bit to assert the external HOREQ...

Page 114: ...ta Reset Type HW Reset SW Reset IR Reset ST Reset ICR 0 INIT 0 0 0 0 HM 1 0 0 0 0 0 TREQ 0 0 0 0 RREQ 0 0 0 0 HF 1 0 0 0 0 0 CVR 1 HC 0 0 0 0 HV 5 0 17 17 17 17 ISR 2 HOREQ 0 0 0 0 DMA 0 0 0 0 HF 3 2 0 0 TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 IVR 3 IV 7 0 0F 0F RXH 5 RXH 23 16 RXM 6 RXM 15 8 RXL 7 RXL 7 0 TXH 5 TXH 23 21 TXM 6 TXM 15 8 TXL 7 TXL 7 0 ...

Page 115: ...ach host processor access If HR W is high and HEN is asserted H 7 0 are configured as outputs and DSP data is transferred to the host processor If HR W is low and HEN is asserted H 7 0 are configured as inputs and host data is transferred to the DSP HR W is stable when HEN is asserted HR W can be configured as a GPIO pin PB11 when the HI is not being used and is configured as a GPIO input pin duri...

Page 116: ...IO this input acts as a GPIO pin called PB14 When the port is defined as the HI the user can manipulate the Port B control register to configure this input as either PB14 or as the HACK pin Table 4 6 shows the Port B Control register bit configurations HACK can act as a data strobe for HI DMA data transfers See Figure 4 18 on page 4 42 Or if HACK is used as an MC68000 host interrupt acknowledge it...

Page 117: ... the only way to reset the appropriate status bits 4 4 7 1 HI Host Processor Data Transfer The HI looks like Static RAM to the host processor Accordingly in order to transfer data with the HI the host processor 1 asserts the Host Address HOA 2 0 to select the register to be read or written 2 asserts HR W to select the HI for the current access and Figure 4 14 Host Processor Transfer Timing HOA0 HO...

Page 118: ...to determine the interrupt source see Figure 4 21 on page 4 45 The host processor interrupt service routine must read or write the appropriate HI register to clear the interrupt HOREQ is deasserted when one of the following occurs the enabled request is cleared or masked DMA HACK is asserted or the DSP is reset 4 4 7 3 Polling In the Polling mode of operation the HOREQ pin is not connected to the ...

Page 119: ... the corresponding mask bit TREQ or RREQ is set This is illustrated in Figure 4 16 Generally servicing the interrupt starts with reading the ISR as described in the previous section on polling to determine which DSP has generated the interrupt and why When multiple DSPs occur in a system the HOREQ bit in the ISR will normally be read first to determine the interrupting device The host processor in...

Page 120: ...st processor asserts HACK with its interrupt acknowledge cycle 1 K DSP56012 IPL2 IPL1 IPL0 D0 D7 HOREQ HACK H0 H7 IACK LOGIC 0F 3 5 V Interrupt Vector Number Interrupt Vector Register IVR Read Write MC68000 1 The DSP56012 Asserts HOREQ to interrupt the host processor IACK Interrupt Vector Register IVR AA0323 11 7 0 AS FC0 FC2 A1 A31 HOREQ Asserted HOREQ AA0324k Status 2 Mask HOREQ HF3 HF2 TRDY TXD...

Page 121: ...MA channel has been initialized HACK is used to strobe the data transfer as shown in Figure 4 17 on page 4 41 where an MC68440 is used as the DMA controller DMA transfers to and from the HI are presented in more detail in Section 4 4 8 Host Interface Application Examples Figure 4 17 DMA Transfer Logic and Timing DMA ACK Gated Off Fast Interrupt To Transfer 24 bit Word High Byte MC68440 IRQ ACK0 5 ...

Page 122: ...r the HC bit by writing the CVR select the data transfer method polling interrupts or DMA see Figure 4 25 on page 4 48 and Figure 4 26 on page 4 50 and write the IVR in the case of an MC680XX family host processor Figure 4 19 on page 4 43 through Figure 4 22 on page 4 46 provide a general description of how to initialize the HI Later paragraphs in this section provide more detailed descriptions of...

Page 123: ...plications STEP 1 of HI Port Configuration 1 Enable Disable Host Receive Data Full Interrupt Enable Interrupt Bit 0 1 Disable Interrupt Bit 0 0 2 Enable Disable Host Transmit Data Empty Interrupt Enable Interrupt Bit 1 1 Disable Interrupt Bit 1 0 3 Enable Disable Host Command Pending Interrupt Enable Interrupt Bit 2 1 Disable Interrupt Bit 2 0 4 Set Clear Host Flag 2 Optional Enable Flag Bit 3 1 D...

Page 124: ...upt Mode For Enable Receive Data Full Interrupt Bit 0 1 Bit 1 0 0 2 Option 4 Load HI Interrupt vector if using the interrupt mode and the host processor requires an interrupt vector AA0328k Enable Transmit Data Empty Interrupt Bit 0 0 Bit 1 1 Enable Receive Data Full Interrupt And Transmit Data Empty Interrupt Bit 0 1 Bit 1 1 Interrupt Vector Register IVR Read Write HF1 HF0 TREQ RREQ 7 0 6 5 4 3 2...

Page 125: ...sfer data at the maximum DSP interrupt rate Figure 4 21 HI Mode and INIT Bits TREQ RREQ INIT Execution 0 0 INIT 0 Address Counter 00 0 1 INIT 0 RXDF 0 HTDE 1 Address Counter 00 1 0 INIT 0 TXDE 1 HRDF 0 Address Counter 00 1 1 INIT 0 RXDF 0 HTDE 1 TXDE 1 HRDF 0 Address Counter 00 Modes 0 0 Interrupt Mode DMA Off 0 1 24 Bit DMA Mode 1 0 16 Bit DMA Mode 1 1 8 Bit DMA Mode Reset Condition Interrupt Mod...

Page 126: ...gure 4 23 HI Configuration Host Side Reserved write as 0 Step 2 of HI Port configuration 2 Option 2 Select polling mode for Host to DSP communication Initialize DSP And HI Port DMA Off Bit 5 0 Bit 6 0 Optional Disable Interrupts Bit 0 0 Bit 1 0 Interrupt Control Register ICR Read Write AA0330k 0 INIT HF1 HF0 TREQ RREQ 7 0 HM0 HM1 6 5 4 3 2 1 Step 2 Of HI Port Configuration 1 Clear Host Command bit...

Page 127: ...be found in 4 4 8 3 DMA Data Transfer and in the DSP56012 Technical Data sheet DSP56012 D Figure 4 24 HI Initialization Host Side DMA Mode 16 bit DMA Bit 5 0 Bit 6 1 0 Reserved write as 0 Initialize DSP Initialize HI Bit 7 1 Optional INTERRUPT CONTROL REGISTER ICR read write DMA off Bit 5 1 Bit 6 1 Step 2 Of Host Port configuration 2 Option 5 Select DMA mode for enable Receive Data Full interrupt ...

Page 128: ...EAD ONLY HRDF HOST RECEIVE DATA FULL 1 THE HOST RECEIVE REGISTER HORX CONTAINS DATA FROM THE HOST PROCESSOR 0 HORX IS EMPTY DMA INDICATES THE HOST PROCESSOR HAS ENABLED THE DMA MODE 1 DMA ON 0 HOST MODE HOST CONTROL REGISTER HCR READ WRITE HRIE HOST RECEIVE INTERRUPT ENABLE ENABLES INTERRUPT AT P 0030 DSP INTERRUPT IS CAUSED BY HRDF 1 1 INTERRUPT P 0030 ENABLED 0 INTERRUPT P 0030 DISABLED TREQ TRA...

Page 129: ...rocessor because the transmit byte registers TXH TXM TXL are empty 2 The host processor can poll as shown in this step 3 Alternatively the host processor can use interrupts to determine the status of this bit Setting the TREQ bit in the ICR causes the HOREQ pin to interrupt the host processor when TXDE is set 4 Once the TXDE bit is set the host can write data to the Host It does this by writing th...

Page 130: ... TXL CLEARS TXDE IN ISR TRANSMIT BYTE REGISTERS TBR 8 WHEN TXDE 0 AND HRDF 0 THEN TRANSFER OCCURS HRDF HOST RECEIVE DATA FULL DMA X FFEB HOST RECEIVE DATA REGISTER HORX 9 THE TRANSFER SETS HRDF FOR THE DSP56012 TO POLL HRIE HOST RECEIVE INTERRUPT ENABLE P 0030 HOST RECEIVE DATA VECTOR FAST INTERRUPT OR LONG INTERRUPT HOREQ HF3 HF2 1 RXDF 7 0 0 DMA 6 5 4 3 2 1 0 0 HF1 HF0 HTDE 0 7 0 0 0 6 5 4 3 2 1...

Page 131: ...nted as a long interrupt the instruction at the interrupt vector location which is not shown is a JSR Since there is only one instruction this could have been implemented as a fast interrupt The MOVEP instruction moves data from the Host to a buffer area in memory and increments the buffer pointer so that the next word received will be put in the next sequential location 4 4 8 2 2 Host to DSP Comm...

Page 132: ...pt VECTOR TABLE HCIE HOST COMMAND INTERRUPT ENABLE P 007E AVAILABLE FOR HOST COMMAND FAST INTERRUPT OR LONG INTERRUPT 1 COMMAND VECTOR REGISTER CVR HC HOST COMMAND STATUS P 0000 HOST COMMAND DEFAULT VECTOR P 0034 AVAILABLE FOR HOST COMMAND AVAILABLE FOR HOST COMMAND interrupt VECTOR ADDRESS HV x 2 1 COMMAND VECTOR REGISTER CVR 1 HOST VECTOR HV 7 0 0 5 X FFE8 HOST CONTROL REGISTER HCR 0 HF3 HF2 HTI...

Page 133: ...d by the DSP CPU to determine if an HC is pending To guarantee a stable interrupt vector write HV only when HC is clear The HC bit and HV can be written simultaneously The host processor can clear the HC bit to cancel a host command at any time before the DSP interrupt is accepted Although the HV can be programmed to any interrupt vector it is not recommended that HV 0 RESET be used because it doe...

Page 134: ... often be used as part of the 16 or 32 bit word The low order byte at 7 should always be written last since writing to it causes the HI to initiate the transfer of the word to the HORX Data is then transferred from the HORX to the DSP program memory If the host processor needs to terminate the bootstrap loading before 512 words have been downloaded it can set the HF0 bit in the ICR The DSP will th...

Page 135: ...F Low BYTE SET HF0 FOR EARLY TERMINATION Because the DSP56012 is so fast host handshaking is generally not required DSP56012 HR W HEN H 7 0 F32 F32 F32 F32 LS09 ADDRESS DECODE 1 K 5 V HOA0 HOA2 LDS AS DTACK A1 A3 D0 D7 R W A4 A23 8 3 MC68000 12 5 MHz MODA IRQA RESET MODB IRQB MDB301 5 V FROM OPEN COLLECTOR BUFFER RESET FUNCTION FROM COLLECTOR BUFFER HACK MODC NMI DR Notes 1 This diode must be a Sc...

Page 136: ...HSR 1 to see when it can send data to the host or it can use interrupts enabled by the HTIE bit in the HCR 2 If HTIE 1 and interrupts are enabled interrupt processing begins at interrupt vector P 0032 3 The interrupt routine should write data to the HOTX 4 which will clear HTDE in the HSR From the host s viewpoint 5 reading the RXL clears RXDF in the ISR When RXDF 0 and HTDE 0 6 the contents of th...

Page 137: ... THE DSP INTERRUPT TO P 0032 0 DISABLE THE DSP INTERRUPT TO P 0032 DSP INTERRUPT IS CAUSED BY HTDE 1 RREQ RECEIVE REQUEST ENABLE USED TO CONTROL THE HOREQ PIN 1 ENABLE INTERRUPT REQUESTS CREATED BY RXDF 0 DISABLE INTERRUPT REQUESTS 2 INTERRUPT STATUS REGISTER ISR READ ONLY 0 X FFE8 HOST STATUS REGISTER HSR READ ONLY HOST CONTROL REGISTER HCR READ WRITE INTERRUPT CONTROL REGISTER ICR READ WRITE X F...

Page 138: ...HTDE 0 THEN TRANSFER OCCURS RXH RXM RXL 7 0 5 6 LAST READ 7 RECEIVE BYTE REGISTERS RBR 2 RXDF RECEIVE DATA FULL 0 RREQ RECEIVE REQUEST ENABLE 8 IF RREQ 1 THEN HOREQ PIN IS ASSERTED TO INTERRUPT HOST HOREQ PIN VIEW FROM HOST 3 IF HTIE 1 AND INTERRUPTS ARE ENABLED THEN INTERRUPT PROCESSING BEGINS 4 DSP56012 WRITES DATA TO HOTX WHICH CLEARS HTDE IN HSR X FFEB HOST TRANSMIT DATA REGISTER HOTX INTERRUP...

Page 139: ... of the DSP addressing modes and modifiers Queues and circular sample buffers are easily created for DMA transfer regions The host interrupts can be programmed as high priority fast or long interrupt service routines The external DMA controller provides the transfers between the DSP HI registers and the external DMA memory The external DMA controller must provide the address to the external DMA me...

Page 140: ...A Characteristics of HI DMA Mode The HOREQ pin is NOT available for host processor interrupts TREQ and RREQ select the direction of DMA transfer DMA to DSP56012 DSP56012 to DMA Simultaneous bidirectional DMA transfers are not permitted Host processor software polled transfers are permitted in the opposite direction of the DMA transfer 8 16 or 24 bit transfers are supported 16 or 24 bit transfers r...

Page 141: ...he HI increments and HOREQ is again asserted Steps 2 5 are then repeated 6 If TXL 7 was written TXDE will be cleared and the address counter in the HI will be loaded with the contents of HM1 and HM0 When TXDE 0 the contents of TXH TXM TXL are transferred to HORX provided that HRDF 0 After the transfer to HORX TXDE will be set and HOREQ will be asserted to start the transfer of another word from ex...

Page 142: ...roller 1 source address byte count direction and other control registers Enable the DMA controller channel 2 Initialize the HI 2 by writing the ICR to select the word size HM0 and HM1 to select the direction TREQ 1 RREQ 0 and to initialize the channel setting INIT 1 see Figure 4 36 on page 4 61 3 The DSP s destination pointer 3 used in the DMA interrupt handler for example an address register must...

Page 143: ...SET TXDE CLEAR HRDF LOAD DMA COUNTER 5 HOST IS FREE TO PERFORM OTHER TASKS i e DSP TO HOST TRANSFER ON A POLLED BASIS 8 TERMINATE DMA CHANNEL 9 TERMINATE DSP DMA MODE BY CLEARING HM1 HM0 AND TREQ 7 DMA CONTROLLER INTERRUPTS HOST WHEN TRANSFERS ARE DONE HOREQ PIN 6 DMA CONTROLLER PERFORMS READS 0 INTERRUPT CONTROL REGISTER ICR 4 ASSERT HOREQ TO START DMA TRANSFER interrupt VECTOR TABLE 3 TELL DSP56...

Page 144: ...1 again on the initial transfer a second host transmit interrupt will be generated immediately and HOTX will be written which will clear HTDE again 3 When RXDF is set the HI s internal DMA address counter is loaded from HM1 and HM0 and HOREQ is asserted 4 The DMA controller enables the data from the appropriate byte register onto H0 H7 by asserting HACK When HACK is asserted HOREQ is deasserted by...

Page 145: ...he DMA transfer from RXH RXM and RXL to the host processor 5 Perform other tasks 5 while the DMA controller transfers data 6 until interrupted by the DMA controller DMA complete interrupt 7 The DSP Interrupt Control Register ICR the Interrupt Status Register ISR and TXH TXM and TXL can be accessed at any time by the host processor but the RXH RXM and RXL registers can not be accessed until the DMA...

Page 146: ...e relationship to DSP clocks There is a minimum HEN deassertion time so that the blocking latch can be updated if the host is in a tight polling loop This minimum time only applies to reading status bits The only potential problem with the host processor s reading of status bits would be its reading HF3 and HF2 as an encoded pair For example if the DSP changes HF3 and HF2 from 00 to 11 there is a ...

Page 147: ...T execution is completed Then start writing reading data If using neither HOREQ for handshaking nor polling the INIT bit wait at least 6T after the deassertion of HEN that wrote the ICR before writing reading data This wait ensures that the INIT is completed because it needs 3T for synchronization worst case plus 3T for executing the INIT 4 4 8 4 7 Unused Pins All unused input pins should be termi...

Page 148: ...4 68 DSP56012 User s Manual MOTOROLA Parallel Host Interface Host Interface HI ...

Page 149: ...MOTOROLA DSP56012 User s Manual 5 1 SECTION 5 SERIAL HOST INTERFACE ...

Page 150: ...Interface 5 1 INTRODUCTION 5 3 5 2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE 5 4 5 4 SERIAL HOST INTERFACE PROGRAMMING MODEL 5 5 5 5 CHARACTERISTICS OF THE SPI BUS 5 19 5 6 CHARACTERISTICS OF THE I2C BUS 5 20 5 7 SHI PROGRAMMING CONSIDERATIONS 5 23 ...

Page 151: ... the SHI can Identify its slave selection in Slave mode Simultaneously transmit shift out and receive shift in serial data Directly operate with 8 16 and 24 bit words Generate vectored interrupts separately for receive and transmit events and update status bits Generate a separate vectored interrupt in the event of a receive exception Generate a separate vectored interrupt in the event of a bus er...

Page 152: ...sfers without going through an intermediate register The single master configuration allows the DSP to directly connect to dumb peripheral devices For that purpose a programmable baud rate generator is included to generate the clock signal for serial transfers The host side invokes the SHI for communication and data transfer with the DSP through a shift register that may be accessed serially using...

Page 153: ... to select the proper clock rate within the range as defined in the I2C and SPI bus specifications 5 4 SERIAL HOST INTERFACE PROGRAMMING MODEL The Serial Host Interface programming model is divided in two parts Host side see Figure 5 3 below and Section 5 4 1 on page 5 8 DSP side see Figure 5 4 on page 5 6 and Sections 5 4 2 on page 5 8 through 5 4 6 on page 5 13 for detailed information Figure 5 ...

Page 154: ... written with 0 for future compatibility HDM5 HFM1 0 7 6 5 4 3 2 1 HFM0 HDM2 HDM0 HDM1 HRS HDM3 HDM4 CPHA CPOL SHI Clock Control Register HCKR X FFF0 0 23 HTX 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 HEN 0 7 6 5 4 3 2 1 HM1 HI 2 C HM0 HRQE0 HMST HRNE HBER HRFF HROE HBUSY HRQE1 HIDLE SHI Control Status Register HCSR HRIE0 HRIE1 HTUE HTDE HTIE X FFF1 FIFO 10 Words Deep HBIE HFIFO 8 15 14 13 12 ...

Page 155: ...le 5 1 SHI Interrupt Vectors Address Interrupt Source P 0020 SHI Transmit Data P 0022 SHI Transmit Underrun Error P 0024 SHI Receive FIFO Not Empty P 0026 Reserved P 0028 SHI Receive FIFO Full P 002A SHI Receive Overrun Error P 002C SHI Bus Error Table 5 2 SHI Internal Interrupt Priorities Priority Interrupt Highest SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FI...

Page 156: ...controlled by the SHI controller logic 5 4 2 SHI Host Transmit Data Register HTX DSP Side The Host Transmit data register HTX is used for DSP to Host data transfers The HTX register is 24 bits wide Writing to the HTX register clears the HTDE flag The DSP may program the HTIE bit to cause a Host transmit data interrupt when HTDE is set see 5 4 6 10 HCSR Transmit Interrupt Enable HTIE Bit 11 on page...

Page 157: ... ignored in the other operational modes HSAR holds five bits of the 7 bit slave address of the device The SHI also acknowledges the general call address all 0s 7 bit address and a 0 R W bit specified by the I2 C protocol HSAR cannot be accessed by the host processor 5 4 4 1 HSAR Reserved Bits Bits 17 0 19 These bits are reserved and unused They read as 0s and should be written with 0s for future c...

Page 158: ... Clock Phase and Polarity CPHA and CPOL Bits 1 0 The programmer may select any of four combinations of Serial Clock SCK phase and polarity when operating in the SPI mode refer to Figure 5 6 on page 5 10 The clock polarity is determined by the Clock Polarity CPOL control bit which selects an active high or active low clock When CPOL is cleared it produces a steady state low value at the SCK pin of ...

Page 159: ...register for transmission as soon as the shift register is empty HTDE is set when the data is transferred from HTX to the shift register When in Master mode and CPHA 0 the DSP core should write the next data word to HTX when HTDE 1 clearing HTDE the data is transferred immediately to the shift register for transmission HTDE is set only at the end of the data word transmission Note The master is re...

Page 160: ...inate undesired spikes that might occur on the clock and data in lines and allow the SHI to operate in noisy environments when required One filter is located in the input path of the SCK SCL line and the other is located in the input path of the data line i e the SDA line when in I2 C mode the MISO line when in SPI Master mode and the MOSI line when in SPI Slave mode When HFM 1 0 are cleared the f...

Page 161: ...individual reset the HCSR status bits are reset to their hardware reset state while the control bits are not affected 5 4 6 1 HCSR Host Enable HEN Bit 0 The read write control bit Host Enable HEN enables the overall operation of the SHI When HEN is set SHI operation is enabled When HEN is cleared the SHI is disabled individual reset state see below The HCKR and the HCSR control bits are not affect...

Page 162: ...0 levels It is recommended that an SHI individual reset be generated HEN cleared before changing HFIFO HFIFO is cleared during hardware reset and software reset 5 4 6 6 HCSR Master Mode HMST Bit 6 The read write control bit HCSR Master HMST determines the operating mode of the SHI If HMST is set the interface operates in the Master mode If HMST is cleared the interface operates in the Slave mode T...

Page 163: ...e correct transmission of the slave device address byte HIDLE should be set only when HTX is empty HTDE 1 After HIDLE is set a write to HTX will clear HIDLE and cause the generation of a stop event a start event and then the transmission of the eight MSBs of the data as the slave device address byte While HIDLE is cleared data written to HTX will be transmitted as is If the SHI completes transmitt...

Page 164: ...pt service routine 5 4 6 10 HCSR Transmit Interrupt Enable HTIE Bit 11 The read write HCSR Transmit Interrupt Enable HTIE control bit is used to enable the SHI transmit data interrupts If HTIE is cleared transmit interrupts are disabled and the HTDE status bit must be polled to determine if the SHI transmit data register is empty If both HTIE and HTDE are set and HTUE is cleared the SHI will reque...

Page 165: ... In this case the SHI will retransmit the previously transmitted word When operating in the SPI mode HTUE is set at the first clock edge if CPHA 1 it is set at the assertion of SS if CPHA 0 If a transmit interrupt occurs with HTUE set the transmit underrun interrupt vector will be generated If a transmit interrupt occurs with HTUE cleared the regular transmit data interrupt vector will be generate...

Page 166: ...rror HROE indicates that a data receive overrun error occurred Receive overrun errors can not occur when operating in the I2 C Master mode since the clock is suspended if the receive FIFO is full HROE is set when the shift register IOSR is filled and ready to transfer the data word to the HRX FIFO and the FIFO is already full HRFF is set When a receive overrun error occurs the shift register is no...

Page 167: ...ogether in a circular manner where one shift register is located on the master side and the other on the slave side Thus the data bytes in the master device and slave device are effectively exchanged The MISO and MOSI data pins are used for transmitting and receiving serial data When the SPI is configured as a master MISO is the master data input line and MOSI is the master data output line When t...

Page 168: ...following rules Data transfer may be initiated only when the bus is not busy During data transfer the data line must remain stable whenever the clock line is high Changes in the data line when the clock line is high will be interpreted as control signals see Figure 5 7 Accordingly the I2C bus protocol defines the following events Bus not busy Both data and clock lines remain high Start data transf...

Page 169: ...e slave transmitter The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse see Figure 5 9 By definition a device that generates a signal is called a transmitter and the device that receives the signal is called a receiver The device that controls the si...

Page 170: ... and 1 indicates a request for data read A data transfer is always terminated by a stop event generated by the master device However if the master device still wishes to communicate on the bus it can generate another start event and address another slave device without first generating a stop event this feature is not supported by the SHI when operating as an I2 C master device This method is also...

Page 171: ...HA and CPOL bits in the HCKR correspond to the external host clock phase and polarity Other HCKR bits are ignored When configured in the SPI Slave mode the SHI external pins operate as follows SCK SCL is the SCK serial clock input MISO SDA is the MISO serial data output MOSI HA0 is the MOSI serial data input SS HA2 is the SS Slave Select input HREQ is the Host Request output In the SPI Slave mode ...

Page 172: ...Ps one operating as an SPI master device and the other as an SPI slave device enables full hardware handshaking if operating with CPHA 1 The SS line should be kept asserted during a data word transfer If the SS line is deasserted before the end of the data word transfer the transfer is aborted and the received data word is lost 5 7 2 SPI Master Mode The SPI Master mode is initiated by enabling the...

Page 173: ...ng from transmit to receive data The HREQ input pin is ignored by the SPI master device if the HRQE 1 0 bits are cleared and considered if any of them is set When asserted by the slave device HREQ indicates that the external slave device is ready for the next data transfer As a result the SPI master sends clock pulses for the full data word transfer HREQ is deasserted by the external slave device ...

Page 174: ...he I2 C bus protocol and is transferred to the HRX FIFO when the complete word according to HM0 HM1 is filled into IOSR It is the responsibility of the programmer to select the correct number of bytes in an I2 C frame so that they fit in a complete number of words For this purpose the slave device address byte does not count as part of the data and therefore it is treated separately In a receive s...

Page 175: ...purpose the slave device address byte does not count as part of the data and therefore it is treated separately In a transmit session only the transmit path is enabled and the IOSR to HRX FIFO transfers are inhibited When the HTX transfers its valid data word to IOSR the HTDE status bit is set and the DSP may write a new data word to HTX If both IOSR and HTX are empty an underrun condition occurs ...

Page 176: ...s bit If the HIDLE status bit is set the DSP writes the slave device address and the R W bit to the most significant byte of HTX The SHI generates a start event The SHI transmits one byte only internally samples the R W direction bit last bit and accordingly initiates a receive or transmit session The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value If acknowledged AC...

Page 177: ...e stop event and terminates the session In a receive session only the receive path is enabled and the HTX to IOSR transfers are inhibited If the HRNE status bit is set the HRX FIFO contains valid data which may be read by the DSP When the HRX FIFO is full the SHI suspends the serial clock just before acknowledge In this case the clock will be reactivated when the FIFO is read the SHI gives an ACK ...

Page 178: ...when the SHI proceeds with the transmit session or HIDLE is set the SHI reactivates the clock to generate the Stop event and terminate the transmit session 5 7 5 SHI Operation During Stop The SHI operation cannot continue when the DSP is in the Stop state since no DSP clocks are active While the DSP is in the stop state the SHI will remain in the individual reset state While in the individual Rese...

Page 179: ...MOTOROLA DSP56012 User s Manual 6 1 SECTION 6 SERIAL AUDIO INTERFACE ...

Page 180: ...6012 User s Manual MOTOROLA Serial Audio Interface 6 1 INTRODUCTION 6 3 6 2 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6 4 6 3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL 6 8 6 4 PROGRAMMING CONSIDERATIONS 6 24 ...

Page 181: ... the serial clock and the word select lines are driven internally according to the baud rate generator programming In the Slave mode these signals are supplied from an external source The transmitter consists of three transmit data registers three fully synchronized output shift registers and three serial data output lines controlled by one transmitter controller This permits data transmission to ...

Page 182: ...ntly or separately The following paragraphs describe the operation of these sections 6 2 1 Baud Rate Generator The baud rate generator produces the internal serial clock for the SAI if either or both of the receiver and transmitter sections are configured in the Master mode The baud rate generator is disabled if both receiver and transmitter sections are configured as slaves Figure 6 1 illustrates...

Page 183: ...l pins are tri stated The block diagram of the receiver section is shown in Figure 6 2 The 24 bit shift registers receive the incoming data from the Serial Data In pins SDI0 and SDI1 or SDIx Data is shifted in at the transitions of the serial receive clock SCKR Data is assumed to be received MSB first if RDIR is cleared and LSB first if RDIR is set Data is transferred to the SAI receive data regis...

Page 184: ...ection equally affect all three transmitters The transmit section can be configured as a master driving its bit clock and word select lines from the internal baud rate generator or as a slave receiving these signals from an external source Each of the three transmitters can be enabled separately When a transmitter is disabled its associated Serial Data Out SDO pin goes to high level When all trans...

Page 185: ...r is considered empty and ready to be reloaded can be 16 24 or 32 bits as determined by the TWL1 and TWL0 control bits in the TCS register A special control mechanism is used to emulate a 32 bit shift register if the word length is defined as 32 bits This is done by enabling eight data shifts at the beginning end of the data word transfer according to the TDWE bit in the TCS register These shift r...

Page 186: ...ns for the SAI are shown in Table 6 1 The interrupts generated by the SAI are prioritized as shown in Table 6 2 Figure 6 4 SAI Registers PM0 0 1 PM2 2 PM3 3 PM4 4 5 PM6 6 PM7 7 PSR 8 9 10 11 12 13 14 15 Baud Rate Control Register BRC R0EN 0 1 RMST 2 RWL0 3 RWL1 4 5 RDIR 6 RLRS 7 RCKP 8 RREL 9 RDWT 10 RXIE 11 12 13 RLDF 14 RRDF 15 Receive Control Status Register RCS T0EN 0 1 TMST 2 TWL0 3 TWL1 4 5 ...

Page 187: ...are defined as slaves or when both are in the individual reset state otherwise improper operation may result When read by the DSP the BRC appears on the two low order bytes of the 24 bit word and the high order byte is read as 0s The BRC is cleared during hardware reset and software reset Table 6 1 SAI Interrupt Vector Locations Interrupt TXIL 0 TXIL 1 RXIL 0 RXIL 1 Left Channel Transmit P 0010 P ...

Page 188: ...S is a 16 bit read write control status register used to direct the operation of the receive section in the SAI see Figure 6 4 on page 6 8 The control bits in the RCS determine the serial format of the data transfers whereas the status bits of the RCS are used by the DSP programmer to interrogate the status of the receiver Receiver enable and interrupt enable bits are also provided in the RCS When...

Page 189: ...igured as a master In the Master mode the receiver drives the SCKR and WSR pins When RMST is cleared the SAI receiver section is configured as a slave In the Slave mode the SCKR and WSR pins are driven from an external source The RMST bit is cleared during hardware reset and software reset 6 3 2 5 RCS Receiver Word Length Control RWL 1 0 Bits 4 and 5 The read write Receiver Word Length RWL 1 0 con...

Page 190: ...nt Bit first see Figure 6 5 The RDIR bit is cleared during hardware reset and software reset 6 3 2 7 RCS Receiver Left Right Selection RLRS Bit 7 The read write Receiver Left Right Selection RLRS control bit selects the polarity of the Receiver Word Select WSR signal that identifies the left or right word in the input bit stream When RLRS is cleared WSR low identifies the left data word and WSR hi...

Page 191: ...he positive edge of the clock and are considered valid during negative transitions of the clock see Figure 6 7 The RCKP bit is cleared during hardware reset and software reset 6 3 2 9 RCS Receiver Relative Timing RREL Bit 9 The read write Receiver Relative timing RREL control bit selects the relative timing of the Word Select Receive WSR signal as referred to the serial data input lines SDIx When ...

Page 192: ...egister When RDWT is set the last 24 bits received are transferred to the data register The RDWT bit is ignored if RWL 1 0 are set for a word length other than 32 bits see Figure 6 9 on page 6 14 The RDWT bit is cleared during hardware reset and software reset Figure 6 8 Receiver Relative Timing RREL Programming Figure 6 9 Receiver Data Word Truncation RDWT Programming MSB LSB LSB MSB SDI WSR MSB ...

Page 193: ...RRDF 1 This means that the previous data in the receive data register was lost and an overrun occurred To clear RLDF or RRDF during Left or Right channel interrupt service the receive data registers of the enabled receivers must be read Clearing RLDF or RRDF will clear the respective interrupt request If the Receive interrupt with exception indication is signaled RLDF RRDF 1 then RLDF and RRDF are...

Page 194: ...st will depend on the state of the receive overrun condition The RLDF bit is cleared during hardware reset and software reset 6 3 2 14 RCS Receiver Right Data Full RRDF Bit 15 Receiver Right Data Full RRDF is a read only status bit which in conjunction with RLDF indicates the status of the enabled receive data register RRDF is set when the right data word as indicated by the WSR pin and the RLRS b...

Page 195: ... the bits in TCS When the T0EN T1EN and T2EN bits are cleared the SAI transmitter section is disabled and it enters the individual reset state after a one instruction cycle delay While in the Stop or individual reset state the status bits in TCS are cleared Stop or individual reset do not affect the TCS control bits The programmer should change TCS control bits except for TXIE only while the trans...

Page 196: ...Bits 4 5 The read write control bits Transmitter Word Length TWL 1 0 are used to select the length of the data words transmitted by the SAI The data word length is defined by the number of serial clock cycles between two edges of the word select signal Word lengths of 16 24 or 32 bits may be selected as shown in Table 6 4 If the 16 bit word length is selected the 16 MSBs of the transmit data regis...

Page 197: ...KP control bit switches the polarity of the transmitter serial clock When TCKP is cleared the transmitter clock polarity is negative Negative polarity means that the Word Select Transmit WST and Serial Data Out SDOx lines change synchronously with the negative edge of the clock and are considered valid during positive transitions of the clock When TCKP is set the transmitter clock polarity is posi...

Page 198: ... together with the last bit of the previous data word as required by the I2 S format see Figure 6 13 The TREL bit is cleared during hardware reset and software reset 6 3 4 10 TCS Transmitter Data Word Expansion TDWE Bit 10 The read write Transmitter Data Word Expansion TDWE control bit selects the method used to expand a 24 bit data word to 32 bits during transmission When TDWE is cleared after tr...

Page 199: ... Clearing TXIE will mask a pending transmitter interrupt only after a one instruction cycle delay If TXIE is cleared in a long interrupt service routine it is recommended that at least one other instruction should be inserted between the instruction that clears TXIE and the RTI instruction at the end of the interrupt service routine There are three different transmit data interrupts that have sepa...

Page 200: ...t is cleared during hardware reset and software reset Refer to Table 6 1 on page 6 9 6 3 4 13 TCS Reserved Bit Bit 13 Bit 13 in TCS is reserved and unused It is read as 0s and should be written with 0 for future compatibility 6 3 4 14 TCS Transmitter Left Data Empty TLDE Bit 14 Transmitter Left Data Empty TLDE is a read only status bit that in conjunction with TRDE indicates the status of the enab...

Page 201: ...TLDE and TRDE are set TRDE is cleared when the DSP writes to the transmit data register of the enabled transmitters provided that When a transmit underrun condition occurs the previous data which is still present in the data registers will be re transmitted In this case TRDE is cleared by first reading the TCS register followed by writing the transmit data registers of the enabled transmitters If ...

Page 202: ...he left word is detected on the WST pin if operating in the Slave mode Note that even though the TRDE and TLDE status flags are always cleared while the transmitter section is in the individual reset state the transmit data registers may be written in this state The data will remain in the transmit data registers while the transmitter section is in the individual reset state and will be transferre...

Page 203: ... unexpected operation might result In particular this can happen when SCKR SCKT runs freely and WSR WST transitions occur earlier or later than expected in terms of complete bit clock cycles In order to explore the SAI reaction in such irregular conditions the operation of the SAI state machine is described here After completion of a data word transfer or upon exiting the individual reset state th...

Page 204: ...t Likewise when the WSR WST transition appears later than expected in the time period between the completion of the previous word and the appearance of the late WSR WST transition the data bits being received are ignored and no data is transmitted These characteristics can be used to disable reception or transmission of undesired data words by keeping SCKR SCKT running freely and gating WSR WST fo...

Page 205: ...MOTOROLA DSP56012 User s Manual 7 1 SECTION 7 GPIO ...

Page 206: ...7 2 DSP56012 User s Manual MOTOROLA GPIO 7 1 INTRODUCTION 7 3 7 2 GPIO PROGRAMMING MODEL 7 3 7 3 GPIO REGISTER GPIOR 7 3 ...

Page 207: ... 1 The register is described in the following paragraphs 7 3 GPIO REGISTER GPIOR The GPIO Register GPIOR is a 24 bit read write control data register used to operate and configure the GPIO pins The control bits in the GPIOR select the direction of data transfer for each pin whereas the data bits in the GPIOR are used to read from or write to the GPIO pins Hardware reset and software reset clear al...

Page 208: ...n bits GDD 7 0 select the direction of data transfer for each of the GPIO 7 0 pins see Table 7 1 When the GDDx bit is cleared the corresponding GPIOx pin is defined as an input When the GDDx bit is set the corresponding GPIOx pin is defined as an output The GDD 7 0 bits are cleared during hardware reset and software reset 7 3 3 GPIOR Control Bits GC 7 0 Bits 23 16 The read write GPIO Control bits ...

Page 209: ...cted to the pin see Table 7 1 and Figure 7 2 When the GCx bit is cleared and the GDDx bit is set the pin is defined as output the corresponding GPIOx pin output buffer is defined as a standard active high active low type see Table 7 1 and Figure 7 2 When the GCx bit is set and the GDDx bit is set the pin is defined as output the corresponding GPIOx pin output buffer is defined as an open drain typ...

Page 210: ...7 6 DSP56012 User s Manual MOTOROLA GPIO GPIO Register GPIOR ...

Page 211: ...MOTOROLA DSP56012 User s Manual 8 1 SECTION 8 DIGITAL AUDIO TRANSMITTER ...

Page 212: ...r s Manual MOTOROLA Digital Audio Transmitter 8 1 OVERVIEW 8 3 8 2 DAX SIGNALS 8 4 8 3 DAX FUNCTIONAL OVERVIEW 8 5 8 4 DAX PROGRAMMING MODEL 8 6 8 5 DAX INTERNAL ARCHITECTURE 8 6 8 6 DAX PROGRAMMING CONSIDERATIONS 8 14 ...

Page 213: ...ck source and this selection configures the DAX to operate in Slave or Master mode Supports both Master mode and Slave mode in a digital audio network If the user selects a divided DSP core clock the DAX will operate in the Master mode If the user selects an external clock source the DAX will operate in the Slave mode The accessible DAX registers are all mapped in the X I O memory space This allow...

Page 214: ... pin The frequency of the external clock must be 256 times 384 times or 512 times the audio sampling frequency 256 Fs 384 Fs or 512 Fs The ACI pin is high impedance during hardware reset and software reset Note If the DAX is not used connect the ACI pin to ground through an external pull down resistor to ensure a stable logic level at the input Figure 8 1 Digital Audio Transmitter DAX Block Diagra...

Page 215: ...t and if DAX interrupt is enabled an interrupt request is sent to the DSP core The interrupt handling routine then stores the next frame of audio data in the XADRA XADRB and the non audio data bits in the XCTR At the beginning of a frame transmission one of the 8 bit Channel A preambles Z preamble for the first sub frame in a block or X preamble otherwise is generated in the preamble generator and...

Page 216: ...the XADRA XADRB and the non audio data bits from the XCTR are uploaded 8 4 DAX PROGRAMMING MODEL The programmer accessible DAX registers are shown in Figure 8 2 on page 8 7 The registers are described in the following subsections The Interrupt Vector table for the DAX is shown in Table 8 1 The internal interrupt priority is shown in Table 8 2 8 5 DAX INTERNAL ARCHITECTURE Hardware components shown...

Page 217: ... holds Channel B audio data for the current frame while Channel A audio and non audio data are being transmitted At the beginning of a frame transmission audio data stored in the XADRA is directly transferred to the XADSR for Channel A transmission and at the same time the Channel B audio data stored in XADRB is transferred to the XADBUF The Channel B audio data in the XADBUF is transferred to the...

Page 218: ...ation It also holds the three bits of non audio data for a frame The contents of the XCTR are shown in Figure 8 2 on page 8 7 The XCTR bits are described in the following paragraphs 8 5 4 1 DAX Enable XEN Bit 0 When the XEN bit is set the DAX is enabled If the DAX Stop XSTP control bit is set XEN is sampled at every frame boundary thus clearing XEN during the middle of a frame transmission will st...

Page 219: ...he next frame Note This bit is not affected by any of the DAX reset states 8 5 4 7 DAX Channel A User Data XUA Bit 11 The value of the XUA bit is transmitted as the thirtieth bit Bit 29 of the Channel A sub frame in the next frame Note This bit is not affected by any of the DAX reset states 8 5 4 8 DAX Channel A Channel Status XCA Bit 12 The value of the XCA bit is transmitted as the thirty first ...

Page 220: ...e the next audio data This bit is set at the beginning of every frame transmission more precisely when an audio data upload from the XADRA XADRB to XADSR XADBUF occurs When XADE is set and the DAX interrupt is enabled XIEN 1 a DAX interrupt request with the Transmit Data Empty interrupt vector is sent to the DSP core Note XADE is cleared by writing data to XADRA and XADRB It is cleared by software...

Page 221: ... shown in Figure 8 3 on page 8 11 8 5 5 5 DAX Transmit In Progress XTIP Bit 4 The XTIP status flag indicates that the DAX is enabled and transmitting data When XTIP is set it indicates that the DAX is active When XTIP is cleared it indicates that the DAX is inactive This bit provides programmers with the means to determine whether the DAX is active or inactive Since the DAX can be active and trans...

Page 222: ...tor PRTYG The PRTYG generates the parity bit for the sub frame being transmitted The generated parity bit ensures that sub frame bits four to thirty one will carry an even number of 1s and 0s 8 5 8 DAX Biphase Encoder The DAX biphase encoder encodes each audio and non audio bit into its biphase mark format and shifts this encoded data out to the ADO output pin synchronous to the biphase clock 8 5 ...

Page 223: ...he DAX clock multiplexer selects one of the clock sources and generates the biphase clock 128 Fs and shift clock 64 Fs The clock source can be selected from the following options see also Section 8 5 4 4 on page 8 9 The internal DSP core clock assumes 1024 Fs DAX clock input pin ACI 512 Fs DAX clock input pin ACI 384 Fs DAX clock input pin ACI 256 Fs Figure 8 5 shows how each clock is divided to g...

Page 224: ... the XCTR transmission begins 8 6 2 Transmit Register Empty Interrupt Handling When the XIEN bit is set and the DAX is active a Transmit Audio Data register Empty interrupt XADE 1 is generated once at the beginning of every frame transmission Typically within an XADE interrupt one frame of audio data to be transmitted in the next frame is stored in the XADRA and the XADRB by two consecutive MOVEP ...

Page 225: ... when the DSP is in the Stop state since no DSP clocks are active While the DSP is in the Stop state the DAX will remain in the individual reset state and the status flags are initialized as described for resets No DAX control bits are affected It is recommended that the DAX be disabled by clearing the XEN bit in the XCTR before the DSP enters the Stop state ...

Page 226: ...8 16 DSP56012 User s Manual MOTOROLA Digital Audio Transmitter DAX Programming Considerations ...

Page 227: ...1 1 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1 0 0 0 0 1 1 0 1 1 0 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 ...

Page 228: ...A 2 DSP56012 User s Manual MOTOROLA Bootstrap ROM Contents A 1 INTRODUCTION A 3 A 2 BOOTSTRAPPING THE DSP A 3 A 3 BOOTSTRAP PROGRAM LISTING A 4 ...

Page 229: ...lues present on the MODC MODB and MODA pins upon exit from reset The bootstrap program evaluates the MA bit first then the MC bit and finally the MB bit to determine which bootstrap method to use MA 0 i e MC MB MA xx0 The bootstrap program immediately terminates by jumping to the program ROM and starts executing the program at location P 0A00 Mode 4 MA 1 and MC 0 i e MC MB MA 0x1 The program loads...

Page 230: ...ET Wake up on bootstrap mode _________ with OnCE port enabled 0 MA 1 0 MC 1 0 MB 1 ______ ______ ______ ______ ______ ______ Download Download Download SHI SPI SHI I2C HOST ___________ ___________ ___________ _______ ________ _______ ________ Switch to Switch to Normal mode Normal mode Goto P 0 Goto P 0A00 _______ _______ ______ ______ Note The internal Program ROM is factory programmed Refer to t...

Page 231: ...Program RAM jclr ma omr exit if MC MB MA xx0 goto Program ROM downld clr a A9 r1 clear a0 Program RAM starting address prepare SHI control value in r1 HEN 1 HI2C 0 HM1 HM0 10 HFIFO 1 HMST 0 HRQE1 HRQE0 01 HIDLE 0 HBIE 0 HTIE 0 HRIE1 HRIE0 00 jset mc omr shild If MC MB MA 1X1 load from SHI hostld is the routine that loads from the parallel Host Interface If MC MB MA 001 the internal Program RAM is ...

Page 232: ...bits The SHI operates in the SPI or in the IIC mode according to the bootstrap mode shild jclr mb omr shi_loop If MC MB MA 101 select SPI mode bset hi2c r1 otherwise select I2C mode shi_loop movep r1 x hcsr enable SHI do 256 _loop2 jclr hrne x hcsr wait for HRX not empty movep x hrx p r0 store in Program RAM _loop2 Exit bootstrap ROM exit clr a a0 r0 r0 points to destination address andi ec omr se...

Page 233: ...MOTOROLA DSP56012 User s Manual B 1 APPENDIX B PROGRAMMING REFERENCE ...

Page 234: ... PLL Control Register PCTL B 18 PARALLEL HOST INTERFACE Port B B 19 DSP Side B 19 Processor Side B 21 SERIAL HOST INTERFACE Slave Address and Clock control Registers HSAR HCKR B 24 Host Data Registers B 25 Control Status Register HCSR B 26 SERIAL AUDIO INTERFACE Receiver Control Status Register RCS B 27 Transmitter Control Status Register TCS B 28 Baud Rate Control and Receive Data Registers B 29 ...

Page 235: ...py these sheets and reuse them for each application development project B 2 PERIPHERAL ADDRESSES Figure B 1 on page B 4 is a memory map of the on chip peripherals showing their addresses in memory B 3 INTERRUPT ADDRESSES Table B 1 on page B 5 lists the interrupt starting addresses and sources B 4 INTERRUPT PRIORITIES Table B 2 on page B 6 lists the priorities of specific interrupts within interrup...

Page 236: ...it Register HORX HOTX X FFEA Reserved X FFE9 Host Interface Status Register HSR X FFE8 Host Interface Control Register HCR X FFE7 SAI TX2 Data Register TX2 X FFE6 SAI TX1 Data Register TX1 X FFE5 SAI TX0 Data Register TX0 X FFE4 SAI TX Control Status Register TCS X FFE3 SAI RX1 Data Register RX1 X FFE2 SAI RX0 Data Register RX0 X FFE1 SAI RX Control Status Register RCS X FFE0 SAI Baud Rate Control...

Page 237: ...ion if RXIL 0 P 001C Reserved P 001E 3 NMI P 0020 0 2 SHI Transmit Data P 0022 0 2 SHI Transmit Underrun Error P 0024 0 2 SHI Receive FIFO Not Empty P 0026 Reserved P 0028 0 2 SHI Receive FIFO Full P 002A 0 2 SHI Receive Overrun Error P 002C 0 2 SHI Bus Error P 002E Reserved P 0030 0 2 HI Receive Data P 0032 0 2 HI Transmit Data P 0034 0 2 HI Command Default P 0036 Available for Host Command P 003...

Page 238: ...lock Transferred P 0054 Available for Host Command P 0056 0 2 DAX Transmit Register Empty P 0058 Available for Host Command P 007E Available for Host Command Table B 2 Interrupt Priorities Within an IPL Priority Interrupt Level 3 Nonmaskable Highest Lowest Hardware RESET Illegal Instruction NMI Stack Error Trace SWI Table B 1 Interrupt Starting Addresses and Sources Continued Interrupt Starting Ad...

Page 239: ... Right Channel Receiver SAI Right Channel Transmitter SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HI Command Interrupt HI Receive Data Interrupt HI Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred DAX Transmit Register Empty Table B 2 Interrupt Priorities Within an IPL Continued Prio...

Page 240: ... AND I xx D 1 2 ASL D parallel move 1 mv 2 mv ASR D parallel move 1 mv 2 mv 0 BCHG n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D BCLR n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D BSET n X aa 1 ea 4 mvb n X pp n X ea n Y aa n Y pp n Y ea n D indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on paralle...

Page 241: ...xxx 1 ea 4 jx JCLR n X ea xxxx 2 6 jx n X aa xxxx n X pp xxxx n Y ea xxxx n Y aa xxxx n Y pp xxxx Table B 3 Instruction Set Summary Sheet 2 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on parallel move co...

Page 242: ...Y pp xxxx n S xxxx LSL D parallel move 1 mv 2 mv 0 LSR D parallel move 1 mv 2 mv 0 LUA ea D 1 4 Table B 3 Instruction Set Summary Sheet 3 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on parallel move cond...

Page 243: ...and X memory data move X ea D1 S2 D2 mv mv S1 X ea S2 D2 xxxxxx D1 S2 D2 A X ea X0 A B X ea X0 B Y memory data move Y ea D mv mv Y aa D S Y ea S Y aa xxxxxx D Table B 3 Instruction Set Summary Sheet 4 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be ...

Page 244: ...D2 S2 D1 xxxx D1 xx D1 MOVE M P ea D 1 ea 2 mvm S P ea S P aa P aa D MOVE P X pp D 1 ea 2 mvp X pp X ea Table B 3 Instruction Set Summary Sheet 5 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on parallel m...

Page 245: ...2 NORM Rn D 1 2 NOT D parallel move 1 mv 2 mv 0 OR S D parallel move 1 mv 2 mv 0 ORI xx D 1 2 REP X ea 1 4 mv X aa Y ea Table B 3 Instruction Set Summary Sheet 6 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition dependi...

Page 246: ...R S D parallel move 1 mv 2 mv TST S parallel move 1 mv 2 mv 0 WAIT 1 n a Table B 3 Instruction Set Summary Sheet 7 of 7 Mnemonic Syntax Parallel Moves Instruction Program Words Osc Clock Cycles Status Request Bits S L E U N Z V C indicates that the bit is unaffected by the operation indicates that the bit may be set according to the definition depending on parallel move conditions indicates that t...

Page 247: ...Interrupt Mask Scaling Mode Reserved Trace Mode Double Precision Multiply Mode Loop Flag 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF T S1 S0 I1 I0 L E U N Z V C Status Register SR Read Write Reset 0300 DM S Mode Register MR Condition Code Register CCR Reserved write as 0 0 SR Status Register SR Note The operation and function of the Status Register is detailed in the DSP56000 Family Manual ...

Page 248: ...et 000000 Register IPR 23 22 21 20 19 18 16 17 0 0 0 0 0 0 0 0 0 0 HPL1 0 0 SAI IPL SHL1 SHL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 SHI IPL HPL1 HPL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 HI IPL ILA2 Trigger 0 Level 1 Neg Edge IRQB Mode IBL1 IBL0 Enabled IPL 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 ILA2 Trigger 0 Level 1 Neg Edge IRQA Mode IAL1 IAL0 Enabled IPL 0 0 No 0 1 Yes 0 1...

Page 249: ... 0 23 22 21 20 0 0 0 0 0 0 Stop Delay 0 128 K T Stabilization 1 16 T Stabilization Bits 5 and 7 through 23 are reserved write as 0 Mode M M M C B A Operating Mode 0 0 0 0 Normal operation bootstrap disabled 1 0 0 1 Bootstrap from HI 2 0 1 0 Wake up in Program ROM address 0B00 3 0 1 1 Reserved 4 1 0 0 Reserved 5 1 0 1 Bootstrap from SHI SPI 6 1 1 0 Reserved 7 1 1 1 Bootstrap from SHI I 2 C PEA RAM ...

Page 250: ...N CSRC Multiplication Factor Bits MF0 MF11 MF11 MF0 Multiplication Factor MF 000 1 001 2 002 3 FFE 4095 FFF 4096 Stop Processing State Bit PSTP 0 PLL Disabled During Stop Processing State 1 PLL Enabled During Stop Processing State PLL Enable Bit PEN 0 Disable PLL 1 Enable PLL Chip Clock Source Bit CSRC 0 Output from Low Power Divider 1 Output from VCO Reserved write as 0 0 0 0 0 Division Factor Bi...

Page 251: ...gister X FFEC Read Write Reset 000000 Port B Control Register PBC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBC Host Control Register HCR HTIE HCIE HRIE HF3 HF2 6 5 4 3 2 1 0 7 23 Reserved write as 0 0 0 0 0 Host Control Register HCR X FFE8 Read Write Reset 00 Host Receive Interrupt Enable HRIE 0 disable 1 enable interrupt on HRDF Host Transmit Interrupt Enable HTIE 0 disable 1 enable interrupt on HTDE ...

Page 252: ...O HF1 read only DMA DMA Status DMA 0 disabled 1 enabled 15 6 5 4 3 2 1 0 10 9 8 7 14 13 12 11 19 18 17 16 23 22 21 20 Receive Middle Byte Receive Low Byte Receive High Byte Host Receive Data Register HORX X FFEB Read Only Reset 000000 Host Receive Data Usually Read by Program Host Receive Data Register HORX 15 6 5 4 3 2 1 0 10 9 8 7 14 13 12 11 19 18 17 16 23 22 21 20 Receive Middle Byte Receive L...

Page 253: ... DMA On 0 Host DSP 1 DSP Host Transmit Request Enable TREQ DMA Off 0 interrupts disabled 1 interrupts enabled DMA On 0 DSP Host 1 Host DSP Host Flags HF0 HF1 Write Only Host Mode Control HM0 HM1 00 DMA off 01 24 Bit DMA 10 16 Bit DMA 11 8 Bit DMA Initialize INIT 0 no action 1 initialize DMA HM1 HV1 HV5 HV0 HV4 HV3 6 5 4 3 2 1 0 7 Reserved write as 0 0 HC Command Vector Register CVR Host Command HC...

Page 254: ...t HOREQ 0 HOREQ deasserted 1 HOREQ asserted DMA IV1 IV5 IV0 IV4 IV3 6 5 4 3 2 1 0 7 Reserved write as 0 IV7 Interrupt Vector Register IVR IV2 Receive Data Register Full RXDF 0 wait 1 read Transmit Data Register Empty TXDE 0 wait 1 write DMA Status DMA 0 DMA disabled 1 DMA enabled Transmitter Ready TRDY 0 data in HI 1 data not in HOST8 Interrupt Vector Register IVR 3 Read Write Reset 0F Interrupt V...

Page 255: ...lly Read by Program 0 7 Receive Low Byte 0 0 0 0 0 0 0 0 4 5 6 7 Transmit Byte Registers 7 6 5 4 Write Only Reset 00 Receive Byte Registers 7 6 5 4 Read Only Reset 00 Host Transmit Data Usually Loaded by Program 7 0 0 7 0 7 Transmit High Byte Not Used Transmit Middle Byte 0 7 Transmit Low Byte 0 0 0 0 0 0 0 0 4 5 6 7 Transmit Byte Registers Processor Side HI Receive Byte Registers ...

Page 256: ...0 0 0 0 0 0 0 0 0 HA4 0 0 0 0 0 0 0 0 0 0 HDM5 HCKR Divider Modulus Select HSAR I 2 C Slave Address Slave address Bits HA6 HA3 HA1 and external pins HA2 HA0 Slave address after reset 1011_HA2_0_HA0 HFM1 HFM0 SHI Noise Reduction Filter Mode 0 0 Bypassed Filter disabled 0 1 Reserved 1 0 Narrow spike tolerance 1 1 Wide spike tolerance HFM0 HFM1 SHI Clock Control Register HCKR SHI Slave Address Regist...

Page 257: ... Transmit X FFF3 Write Only Reset xxxxxx Data Register HTX 19 18 17 16 23 22 21 20 Host Transmit Data Register Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHI Host Receive X FFF3 Read Only Reset xxxxxx Data Register HRX 19 18 17 16 23 22 21 20 Host Receive Data Register Contents SHI Host Receive Data Register HRX SHI Host Transmit Data Register HTX ...

Page 258: ...eive SPI Asserted if OISR ready to transmit and receive HIDLE Description 0 Bus busy 1 Stop event HBIE Description 0 Bus Error Interrupt disabled 1 Bus Error Interrupt enabled HTIE Description 0 Transmit Interrupt disabled 1 Transmit Interrupt activated Host Transmit Underrun Error Read Only Status Bit Host Transfer Data Empty Read Only Status Bit Host Receive FIFO Not Empty Read Only Status Bit H...

Page 259: ...SR low identifies Left data word WSR high identifies Right data word 1 WSR high identifies Left data word WSR low identifies Right data word RCKP Description 0 Polarity is negative 1 Polarity is positive RREL Description 0 WSR occurs with first bit 1 WSR occurs 1 cycle earlier RDWT Description 0 First twenty four bits transferred 1 Last twenty four bits transferred RXIL Description 0 Rx interrupt ...

Page 260: ...iption 0 WST low identifies Left data word WST high identifies Right data word 1 WST high identifies Left data word WST low identifies Right data word TCKP Description 0 Polarity is negative 1 Polarity is positive TREL Description 0 WSR occurs with first bit 1 WSR occurs 1 cycle earlier TDWE Description 0 Last bit transmitted eight times 1 First bit transmitted eight times TXIE Description 0 Trans...

Page 261: ...ta X FFE3 Read Only Reset xxxxxx Register 1 RX1 19 18 17 16 23 22 21 20 Receive Data Register 1 Contents SAI Receive Data Register 1 RX1 SAI Receive Data Register 0 RX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Baud Rate Control X FFE0 Reset 0000 Register BRC PM0 PM1 PM3 0 PM4 0 0 0 0 0 0 PM2 0 PM5 PM7 PSR PM6 PSR Description 0 Divide by 8 prescaler operational 1 Divide by 8 prescaler bypassed Prescal...

Page 262: ...Data Register 2 Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAI Transmit Data X FFE5 Write Only Reset xxxxxx Register 0 TX0 19 18 17 16 23 22 21 20 Transmit Data Register 0 Contents 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SAI Transmit Data X FFE6 Write Only Reset xxxxxx Register 1 TX1 19 18 17 16 23 22 21 20 Transmit Data Register 1 Contents SAI Transmit Data Register 2 TX2 SAI Transmit Data Regi...

Page 263: ... 3 2 1 0 GD3 GD2 GD1 GD0 GPIO Control Data X FFF7 Reset 000000 Register GPIOR 19 18 17 16 23 22 21 20 GC3 GDD3 GDD2 GDD1 GDD0 GC1 GCx GDDx GPIO Pin Definition 0 0 Disconnected 0 1 Standard output 1 0 Input 1 1 Open drain output GC0 GC2 GPIO Data Bits GD4 GD5 GD6 GD7 GDD7 GDD6 GDD4 GDD4 GC7 GC5 GC4 GC6 GPIO Control Data Register GPIOR ...

Page 264: ...upt Enable 0 DAX interrupts disabled 1 DAX interrupts enabled XSTP DAX Stop Control 0 DAX stops immediately 1 DAX stops after current frame XCS1 XCS0 DAX Clock Source 0 0 DSP Core Clock f 1024 x fs 0 1 ACI Pin f 256 x fs 1 0 ACI Pin f 384 x fs 1 1 ACI Pin f 512 x fs Channel A Validity XVA Channel A User Data XUA Channel A Status XCA Channel B Validity XVB Channel B User Data XUB Channel B Status X...

Page 265: ...lidity XVA bit 8 9 DAX Channel B Channel Status XCB bit 8 10 DAX Channel B User Data XUB bit 8 10 DAX Channel B Validity XVB bit 8 9 DAX Clock input Select bits 8 9 DAX clock multiplexer 8 13 DAX clock selection 8 9 DAX Control Register XCTR 8 8 DAX Enable XEN bit 8 8 DAX internal architecture 8 6 DAX Interrupt Enable XIEN bit 8 8 DAX Non Audio Data Buffer XNADBUF 8 12 DAX Operation During Stop 8 ...

Page 266: ... Flag 1 HF1 bit 4 17 HI Flag 2 HF2 bit 4 15 HI Flag 3 HF3 bit 4 15 HI Pins Host Enable HEN 4 35 host read write HR W 4 35 HI pins Host Acknowledge PB14 HACK 4 36 Host Acknowledge pin PB14 HACK 4 36 Host Address pins HOA0 HOA2 4 35 Host Data Bus pins H0 H7 4 35 Host Request PB13 HOREQ 4 35 HI Receive Data Full HRDF bit 4 16 HI Receive data register HORX 4 18 HI Receive Interrupt Enable HRIE bit 4 1...

Page 267: ...de 5 26 Slave Mode 5 25 Start and Stop Events 5 21 Transmit Data In Master Mode 5 29 Transmit Data In Slave Mode 5 27 I2 C Bus Acknowledgment 5 21 I2 C Mode 5 3 I2 S Format 1 19 I2S Format 6 3 ICR register 4 24 bit 0 Receive Request Enable bit RREQ 4 24 bit 1 Transmit Request Enable bit TREQ 4 24 bit 3 Host Flag 0 bit HF0 4 25 bit 4 Host Flag 1 bit HF1 4 26 bit 5 6 Host Mode Control bits HM1 HM0 4...

Page 268: ...See Appendix B PSR BRC Prescaler Range 6 10 R R0EN RCS Receiver 0 Enable 6 10 R1EN RCS Receiver 1 Enable 6 11 RCKP RCS Receiver Clock Polarity 6 13 RCS Receiver Control Status Register 6 10 RDIR RCS Receiver Data Shift Direction 6 12 RDWT RCS Receiver Data Word Truncation 6 14 Receive Byte registers RXH RXM RXL 4 32 Receive Data Register Full bit RXDF 4 30 Receive Request Enable bit RREQ 4 24 rese...

Page 269: ...it Data Registers 6 23 Transmit Section 6 6 Transmit Section Block Diagram 6 7 Transmitter Clock Polarity Programming 6 20 Transmitter Control Status Register TCS 6 17 Transmitter Data Shift Direction Programming 6 19 Transmitter Data Word Expansion Programming 6 21 Transmitter Left Right Selection Programming 6 19 Serial Audio Interface See Section 6 Serial Audio Interface SAI 1 10 1 19 6 3 Seria...

Page 270: ...Data Shift Direction 6 18 TDWE TCS Transmitter Data Word Expansion 6 20 Timing Skew 1 12 TLDE TCS Transmitter Left Data Empty 6 22 TMST TCS Transmitter Master 6 18 Transmit Byte Registers TXH TXM TXL 4 33 Transmit Data Register Empty bit TXDE 4 31 Transmit Request Enable bit TREQ 4 24 Transmitter Ready bit TRDY 4 31 TRDE TCS Transmitter Right Data Empty 6 23 TRDY bit 4 31 TREL TCS Transmitter Rela...

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