Functional Description
4-20
4
I/O port offset 0Fh: FPGA register data port
All communication of data from the CPV5000 is implemented through the
FPGA register data port. The function of each bit is dependent on the data in
the I/O port offset 0Dh: FPGA register index port.
Watchdog register: FPGA index - 03h
The watchdog timer is designed to be used in critical control applications. The
function of the watchdog is to stop a program or part of the hardware from
going into a runaway or locked out mode.
Watchdog index mode
When the timer is enabled, the watchdog strobe register must be written to at
regular intervals to stop the watchdog from triggering. The exact data that is
written is irrelevant. It is the write operation to the register that resets the
watchdog timer.
The watchdog has four modes when triggered:
1. Disabled
2. Set the WD bit in the watchdog strobe register (073h)
3. Item 2 + Assert IOCHK
4. Item 3 + Reset the CPV5000.
The watchdog is enabled by writing 03h to ISA I/O offset 00Dh (Index), then
writing data to the control register at ISA I/O offset 00Fh.
Table 4-14. FPGA register data port
Bit
7
6
5
4
3
2
1
0
Function
Data from or to the selected FPGA register
Summary of Contents for CPV5000
Page 1: ...CPV5000 CompactPCI Single Board Computer Installation and Reference Guide CPV5000A IH3 ...
Page 16: ...xvi ...
Page 22: ...CPV5000 Single Board Computer Overview 1 6 1 ...
Page 26: ...Getting Started 2 4 2 Figure 2 1 Installing the CPV5000 ...
Page 80: ...Functional Description 4 24 4 ...
Page 108: ...Power On Self Tests 6 18 6 ...
Page 144: ......
