Motorola CPV5000 Installation And Reference Manual Download Page 61

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I/O address map

4-5

Table 4-3.

I/O addresses

Address

Function

0000-000F

DMA controller 1

0020-0021

Interrupt controller 1

0040-0043

Counter timer

0060-0064

Keyboard, NMI, speaker

0070-0071

Real time clock/NMI mask

0050-0057

LM78 System monitor (opt)

0058-005F

WatchDog timer, ENUM (opt)

0080-009F

DMA page register, POST checkpoint

00A0-00BF

Interrupt controller 2

00C0-00DF

DMA controller 2

00F0

Reset coprocessor

0170-0177

Secondary IDE channel (opt)

01F0-01F7

Primary IDE channel

0278-027F

Parallel port 2 (opt)

02E8-02EF

Serial port 4 (opt)

02F8-02FF

Serial port 2 (default)

0376-0377

Secondary IDE port (opt)

0378-037F

Parallel port 1 (default)

03BC-03C3

Parallel port 3 (opt)

03E8-03EF

Serial port 3 (opt)

03F0-03F5

Floppy channel

03F6-03F7

Primary IDE and floppy

03F8-03FF

Serial port 1 (default)

040A-043F

DMA scatter/gather

0480-048F

DMA high pages

04D0-04D1

Edge/level interrupts

04D6

DMA2 extended mode

Summary of Contents for CPV5000

Page 1: ...CPV5000 CompactPCI Single Board Computer Installation and Reference Guide CPV5000A IH3 ...

Page 2: ...rior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Right...

Page 3: ...is a registered trademark of Novell Inc in the U S and other countries AMIBIOS is a trademark of American Megatrends Inc SCO and the SCO logo are trademarks or registered trademarks of The Santa Cruz Corporation Inc in the U S and other countries UNIX is a registered trademark of Open Group in the U S and other countries WATCHDOG is a trademark of National Semiconductor Corporation All other produ...

Page 4: ... or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust A...

Page 5: ...mply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 CISPR 22 Radio Frequency Interference Class B EN50082 1 IEC801 2 IEC801 3 IEC801 4 Electromagnetic Immunity The product also fulfills EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC This board product was tested in a re...

Page 6: ...nufacturer s instructions ATTENTION Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constructeur Mettre au rebut les batteries usagées conformément aux instructions du fabricant VORSICHT Explosionsgefahr bei unsachgemäβem Austausch der Batterie Ersatz nur durch denselben oder eine...

Page 7: ...0 2 2 Installation instructions 2 3 Powering up the CPV5000 2 5 Coin Battery 2 5 Front panel 2 6 Chapter 3 Connectors and Components on the CPV5000 Components 3 1 Connecting to and configuring headers 3 3 CPU speed settings 3 4 CPU Voltage Settings 3 5 Ethernet configuration 3 5 USB configuration 3 6 Front panel connectors 3 6 Rear I O connectors 3 7 On board connectors 3 7 Connectors J4 and J5 3 ...

Page 8: ... connector 3 16 EIDE hard drive connectors 3 17 Floppy connector 3 19 PS 2 keyboard mouse connector 3 21 Serial ports COM1 and COM2 connectors 3 22 Fan power connector 3 23 USB ports 1 and 2 3 23 Ethernet connector 3 24 SCSI connector 3 25 Video connector 3 27 Reset switch 3 28 Chapter 4 Functional Description Peripheral component interconnect PCI local bus 4 1 PCI device mapping and routing 4 2 P...

Page 9: ...elay 4 22 ENUM status and control register FPGA index 11h 4 22 ENUM status and control 4 22 ENUM storage register FPGA index 12h 4 23 Chapter 5 Installing Options System memory configurations 5 1 Installing DRAM SIMMs 5 3 Installation instructions 5 3 Upgrading the CPU 5 4 Installation instructions 5 4 Removing and replacing the battery 5 6 Installing the on board disk drives 5 7 Installation inst...

Page 10: ...and click interface 7 2 Mouse support 7 2 Memory test tick sound 7 3 Using a mouse with WinBIOS Setup 7 3 Using the keyboard with WinBIOS Setup 7 4 WinBIOS Setup main menu 7 5 WinBIOS Setup types 7 6 Standard Setup 7 6 Date time 7 6 Floppy drive A and B 7 6 Pri Master Pri Slave Sec Master Sec Slave 7 7 Configuring an MFM drive 7 7 User defined drive 7 8 Configuring IDE drives 7 9 Configuring a CD ...

Page 11: ... readoff 7 17 Turnaround insertion 7 17 NA Disable NAD for external cache 7 18 Extended cachebility 7 18 ECC test enable 7 18 DRAM data integrity mode 7 18 Bad parity on uncorrectable err 7 19 SERR output type 7 19 SERR duration mode 7 19 Power Management Setup 7 19 Power management 7 19 Instant on support 7 19 Green PC monitor power state 7 19 Video power down mode 7 20 Hard disk power down mode ...

Page 12: ...ral setup 7 24 Onboard FDC 7 24 Onboard serial port 1 COM 1 7 24 Onboard serial port 2 COM 2 7 25 Onboard parallel port 7 25 Parallel port mode 7 25 Parallel port DMA 7 25 Onboard IDE 7 26 Utility menu 7 26 Detect IDE 7 26 Language 7 26 Security 7 27 Supervisor and user icons 7 27 Two levels of passwords 7 27 Setting a password 7 28 Changing a password 7 28 Remember the password 7 28 Anti Virus 7 ...

Page 13: ...ors 3 5 Table 3 6 Rear I O connectors 3 6 Table 3 7 On board connectors 3 6 Table 3 8 J4 connector pin assignments 3 7 Table 3 9 J5 connector pin assignments 3 11 Table 3 10 Parallel connector pin assignments 3 15 Table 3 11 EIDE connector pin assignments 3 16 Table 3 12 Floppy connector pin assignments 3 18 Table 3 13 Keyboard mouse connector pin assignments 3 20 Table 3 14 COM1 and COM2 pin assi...

Page 14: ...ta port when I O port 75h FPGA register index port 01h 4 23 Table 4 19 ENUM Storage 4 24 Table 5 1 Memory configurations 5 2 Table 5 2 CPU speed settings 5 5 Table 6 1 BIOS error reporting 6 2 Table 6 2 Beep codes 6 3 Table 6 3 AMIBIOS error messages 6 4 Table 6 4 ISA NMI handler messages 6 7 Table 6 5 Uncompressed initialized codes 6 9 Table 6 6 Runtime checkpoint codes 6 10 Table 6 7 Bus checkpo...

Page 15: ...xv Table 7 9 External cache 7 15 Table 7 10 System BIOS shadow cacheable 7 16 Table 7 11 Parallel port mode 7 26 ...

Page 16: ...xvi ...

Page 17: ...that the 5V power supply ramp up at the same time or before the 3 3V supply does Introduction The CPV5000 is a CompactPCI PCI Industrial Computer Manufacturers Group PICMG compatible Single Board Computer SBC The CPV5000 is available with a 64 bit Pentium P55C processor or an AMD K 6 processor The CPV5000 s 6U 8HP Compact PCI standard form factor is designed for installation into PICMG CompactPCI ...

Page 18: ... available through rear I O and dual connectors on front panel PS 2 keyboard and mouse connector Video signals available through rear I O and the front panel Ultra SCSI support via AIC7880 SCSI signals available through rear I O and front panel connector Ethernet 10 100 Intel 82558 Ether Express Pro compatible Green PC modes standby and suspend Video power down modes standby and suspend IDE power ...

Page 19: ...n CPV5000 CPV5000 Transition Module Front Panel On board On board Rear Panel Speaker N A Header Reset Push button Header Disk active LED Green Header IDE interface 44 2x22 pin header Two 40 pin headers Floppy disk interface 26 pin 34 pin header Bi directional EPP ECP parallel port 25 pin micro D 25 pin D Serial port 1 16550 9 pin micro D 9 pin D Serial port 2 16550 9 pin micro D 9 pin D PS 2 keybo...

Page 20: ...DIN Micro D Micro D Micro D Ethernet 10 100 Ultra SCSI 7880 Video South Bridge PIIx3 Ultra I O Bridge J1 J2 J4 J5 North DRAM 512K Cache PCI Bus 256M 4 SIMMS with Extended Cacheability Bridge TXC 430HX LM78 System Monitor On board IDE Hard Drive or Flash On board Floppy PCI Bus COM1 COM2 LTP1 Kbd Mouse USBx2 EIDE EIDE Floppy SCSI 3 SVGA Ethernet IDE ...

Page 21: ... condition a flag can be set in a register or an interrupt can be generated System Monitoring LM78 The LM78 is a highly integrated data acquisition system for hardware monitoring of a microprocessor based system On the CPV5000 the LM78 monitors backplane and CPU voltage CPU temperature user definable threshold fan rotation CPU chassis and intrusion with status interrogated through local NMI or SMI...

Page 22: ...CPV5000 Single Board Computer Overview 1 6 1 ...

Page 23: ...e to electrostatic discharge ESD and can easily be damaged Motorola recommends that you use an antistatic wrist strap when handling the CPV5000 and associated components In addition follow these rules Do not allow any circuit board or component to touch non conductors Make sure that your clothing does not make contact with any circuit board or component Keep any loose circuit boards inside or on t...

Page 24: ...MMs Refer to Chapter 3 and Chapter 4 for information about the SIMM headers and the installation of main memory SIMMs A minimum of two identical main memory SIMMs are required The SIMMs may be installed in either bank Set the CPU speed using J10 J14 J15 J29 refer to CPU speed settings page 3 4 Set the CPU type AMD Intel using J30 refer to CPU Voltage Settings page 3 5 Warning Make sure that you di...

Page 25: ...ill that slot 4 Install the top and bottom edge of the CPV5000 in the guides of the chassis 5 Ensure that the levers of the two injector ejectors are in the inward position 6 Slide the CPV5000 into the chassis until resistance is felt 7 Simultaneously move the injector ejector levers in an outward direction 8 Verify that the CPV5000 is properly seated and secure it to the chassis using the two scr...

Page 26: ...Getting Started 2 4 2 Figure 2 1 Installing the CPV5000 ...

Page 27: ...e CPV5000 will enter the Basic Input Output System BIOS setup after completing the memory test If the BIOS setting for quick boot is enabled the memory test may have completed before the VGA has initialized fully Refer to Chapters 6 and 7 for more information about start up tests and BIOS setup The initial boot sequence is complete when the BIOS is displayed Coin Battery The Real time clock and CM...

Page 28: ... lights on the front panel display power hard disk activity watchdog alarm and speaker status Figure 2 2 Front panel connectors and LEDs 2172 9803 RESET CompactPCI CPV5000 SBC USB S C S I FLOPPY V I D E O C O M 1 C O M 2 N E T W O R K SPKR ALARM HDD PWR Keyboard Mouse USB Indicator lights Reset Parallel printer Video SCSI Floppy drive COM1 2 Ethernet ...

Page 29: ... location of the connectors and headers Table 3 1 Major chip functions Reference Description Manufacturer Part Number U20 Ethernet Intel S82557 U24 PCI PCI Bridge Digital 21150 AA U40 Ultra I O SMC FDC37C932 U28 Video Cirrus Logic GD5446 HC A U38 SCSI Adaptor Adaptec AIC 7880P U29 PCI ISA Bridge Intel SB82371SB U43 PCI Host Bridge Intel FW82439HX ...

Page 30: ...ion of main components on the CPV5000 J6 J14 J9 J15 J30 J1 J2 J4 J5 BIOS CPCI ETHERNET J8 J7 CPU VIDEO J12 ULTRA I O SCSI J17 J23 J22 J21 J18 J19 BRIDGE FPGA J29 J10 BATTERY MEMORY SIMMs NORTH BRIDGE CACHE CACHE IDE FLOPPY J13 BANK 1 BANK 0 SOUTH BRIDGE U27 U26 J16 ...

Page 31: ...gh the CPV5000 s front panel and the rear transition module you can use either the front or the rear not both Please note the following cautions when connecting peripherals to the CPV5000 Warning Always remove power from the system before connecting peripherals to the CPV5000 To reduce the risk of personal injury disconnect the power cord from the power source Only qualified experienced electronic...

Page 32: ...for different speed CPUs Install a shorting block across two pins on each of the four speed configuration jumpers to configure any given speed Table 3 2 CPU speed settings CPU Speed J10 J15 J14 J29 166 Mhz 2 3 1 2 1 2 2 3 200 Mhz 2 3 2 3 1 2 2 3 233 Mhz 2 3 2 3 2 3 2 3 266 Mhz 2 3 1 2 2 3 1 2 300 Mhz 2 3 1 2 1 2 1 2 ...

Page 33: ...he AMD processors Figure 3 2 J30 CPU Voltage Settings Ethernet configuration The Ethernet configuration jumper is a three by four jumper block A four position shorting block is installed to select the Ethernet routing To maintain signal integrity the Ethernet signals can be routed to the front connector or the rear connector but not both Table 3 3 indicates which side the shorting block should be ...

Page 34: ...k should be installed to select the front or rear connector Front panel connectors Table 3 5 specifies the connectors that are available from the front panel Table 3 4 USB configuration jumpers Jumper J27 USB Routing Installed Rear connector Removed Front connector Table 3 5 Front panel connectors Location Type Description J23 25 pin micro D Parallel connector J22 2x9 pin micro D Serial port 1 ser...

Page 35: ... J10 2x9 pin D SUB Serial port 1 serial port 2 J13 RJ45 connector Ethernet connector J17 68 pin high density connector SCSI connector J16 15 pin high density D SUB Video connector J2 10 pin unshrouded connector Miscellaneous LM78 inputs J12 2x4 pin USB USB port 1 USB port 2 J14 6 pin PS 2 female connector Keyboard mouse PS 2 connector J15 6 pin PS 2 female connector Mouse PS 2 connector J7 4 pin l...

Page 36: ...w A 25 GND VCC NC NC NC NC GND 24 GND BTI GND DASP b CS3FX b CS1FX b GND 23 GND DA2b DA0b GND DA1b IOCS16 b GND 22 GND INTRQb DMAK b NC IORDYb GND GND 21 GND DIOR b GND DIOW b GND DMARQb GND 20 GND PDIAG b GND DD15b DD0b DD14b GND 19 GND DD1b DD13b DD2b DD12b DD3b GND 18 GND DD11b DD4b DD10b DD5b DD9b GND 17 GND DD6b DD8b DD7b GND DRESET b GND 16 GND GND ERX ERX ETX ETX GND 15 GND EACT ELINK VCC V...

Page 37: ...8 register LM78 pin 15 SSDA LM78 I2C serial data I O SSCL LM78 I2C serial clock input Ethernet RS422 levels ERX differential receive line pair CPV5000 requires transformer to connect to network ETX differential transmit line pair CPV5000 requires transformer to connect to network EACT Ethernet activity LED signal TTL active low ELINK Ethernet link LED signal TTL active low EIDEb ATA 2 TTL levels I...

Page 38: ...rive 1 and monitored by drive 0 SCSI X3T10 SPI single ended levels ATN Attention BSY Busy C D Command or Data I O Input or Output data direction MSG Message phase ACK Acknowledge SCD 15 0 SCSI data lines SCDPH SCSI parity high byte provides parity for SCD 15 8 SCDPL SCSI parity low byte provides parity for SCD 7 0 SEL Select REQ Request SRST SCSI bus reset GND NDET narrow detect may be pulled low ...

Page 39: ...4 and J5 3 11 3 VGA Video VGA levels BLUE blue signal HSYNC horizontal sync GREEN green signal RED red signal VSYNC vertical sync DDCDAT VESA Display Data Channel data I2C DDCCLK VESA Display Data Channel clock I2C ...

Page 40: ...DCLK KBDDAT GND 20 GND SMBCLK GND SMBALERT SMDATA VCC 1 GND 19 GND UDATA0 UDATA0 VCC 2 GND STB GND 18 GND VCC 2 GND UDATA1 UDATA1 AFD GND 17 GND PD0 ERR PD1 INIT PD2 GND 16 GND SLIN PD3 PD4 PD5 PD6 GND 15 GND PD7 ACK BUSY PE SLCT GND 14 GND DTRa GND RIa CTSa RTSa GND 13 GND TXDa DSRa RXDa VCC DCDa GND 12 GND DTRb VCC RIb CTSb RTSb GND 11 GND TXDb DSRb RXDb GND DCDb GND 10 GND DSKCHG HDSEL RDATA WP...

Page 41: ...ector may have pull up on host card PBRESET push button system reset input pulled up filtered and debounced on host card RESET system reset output TTL totem pole on CPV5000 asserted only when 5V power is out of tolerance and upon manual reset push button assertion AUXCLK clock for PS 2 auxiliary device mouse AUXDAT serial data line for PS 2 auxiliary device mouse KBDCLK clock for PC AT or PS 2 key...

Page 42: ...r end indicates the printer is out of paper AFD auto feed causes printer to line feed INIT initializes the printer SLIN select in selects the printer STB data strobe indicates data is valid SLCT select peripheral indicates it is selected CTS clear to send DCD data carrier detected DSR data set ready DTR data terminal ready RI ring indicator RTS request to send RXD serial receive data TXD serial tr...

Page 43: ... IOCS16 indicates a 16 bit register has been decoded DMARQ drive DMA request DMAK drive DMA acknowledge DIOR drive I O read DIOW drive I O write DASP drive active slave present IORDY indicates drive is ready for I O cycle s DD 15 0 drive data lines bits 15 0 DRESET reset signal to drive CS1FX chip select drive 0 also command register block select CS3FX chip select drive 1 also command register blo...

Page 44: ...l connector pin assignments Pin Number Signal Mnemonic Signal Description 1 STROBE Data at parallel port is valid 2 D0 Data bus bit 0 3 D1 Data bus bit 1 4 D2 Data bus bit 2 5 D3 Data bus bit 3 6 D4 Data bus bit 4 7 D5 Data bus bit 5 8 D6 Data bus bit 6 9 D7 Data bus bit 7 10 ACK Acknowledge data retrieval 11 BUSY Printer cannot accept any more data 12 PE Paper error 13 SELECT Set high when select...

Page 45: ...cription 1 RESET Reset signal to drive 23 IOW Drive I O write 2 GND Ground 24 GND Ground 3 DD7 Data Bus Bit 7 25 IOR Drive I O read 4 DD8 Data Bus Bit 8 26 GND Ground 5 DD6 Data Bus Bit 6 27 IORDY IDE I O channel ready 6 DD9 Data Bus Bit 9 28 NC Not connected 7 DD5 Data Bus Bit 5 29 DMACK Drive DMA acknowledge 8 DD10 Data Bus Bit 10 30 GND Ground 9 DD4 Data Bus Bit 4 31 IRQ 10 DD11 Data Bus Bit 11...

Page 46: ...Bus Bit 0 39 DASP Drive active slave present 18 DD15 Data Bus Bit 15 40 GND Ground 19 GND Ground 41 5V 20 NC Not connected 42 5V 21 DMARQ Drive DMA request 43 GND Ground 22 GND Ground 44 NC Not connected Table 3 11 EIDE connector pin assignments Continued Pin Number Signal Mnemonic Signal Description Pin Number Signal Mnemonic Signal Description ...

Page 47: ...h drives should be jumper configured as drive one Table 3 12 Floppy connector pin assignments Pin Number Signal Mnemonic Signal Description 1 5V Drive power 2 INDEX Beginning of a track 3 5V Drive power 4 DSO Drive select 0 5 5V Drive power 6 DSKCHG Notifies disk controller the drive door has opened 7 NC Not connected 8 NC Not connected 9 NC Not connected 10 MTR0 Motor enable outputs 11 NC Not con...

Page 48: ...ck 0 21 GND Ground 22 WPROT Indicates a disk is write protected 23 GND Ground 24 RDATA Raw red data from disk drive 25 GND Ground 26 HDSEL Determines the side of floppy disk being accessed Table 3 12 Floppy connector pin assignments Continued Pin Number Signal Mnemonic Signal Description ...

Page 49: ...on module has two connectors for the keyboard and mouse Note Power present on the J15 connector is only for use by a keyboard pointing device Table 3 13 Keyboard mouse connector pin assignments Pin Number Signal Mnemonic Signal Description 1 KBDDAT Data line for keyboard 2 MDAT Data line for mouse 3 GND Ground 4 KBDVCC Keyboard power current limited to 75 Amp 5 KBDCLK Clock for keyboard 6 MCLK Clo...

Page 50: ...es COM1 and COM2 are 9 pin micro D connectors located on the CPV5000 front panel and regular D connectors on the transition module Table 3 14 COM1 and COM2 pin assignments Pin Number Signal Mnemonic Signal Description 1 DCD Data Carrier Detect 2 RX Receive Data 3 TX Transmit Data 4 DTR Data Terminal Ready 5 GND Signal Ground 6 DSR Data Set Ready 7 RTS Request to Send 8 CTS Clear to Send 9 RI Ring ...

Page 51: ...t panel or the transition module s rear panel Table 3 15 Fan power pin assignments Pin Number Signal 1 5V 2 Tach 3 Ground 4 12V Table 3 16 USB ports pin assignments Pin Number Signal Mnemonic Signal Description 1 5V Current limited USB power 2 DATA USB serial communications differential pair 3 DATA 4 Ground USB port common ...

Page 52: ...h the CPV5000 s front panel or the transition module s rear panel Table 3 17 Ethernet connector pin assignments Pin Number Signal Mnemonic Signal Description 1 TX Transmit data 2 TX Transmit data return 3 RX Receive data 4 NC Not connected 5 NC Not connected 6 RX Receive data 7 NC Not connected 8 NC Not connected ...

Page 53: ...ata bus bit 0 7 GND Ground 41 D1 SCSI data bus bit 1 8 GND Ground 42 D2 SCSI data bus bit 2 9 GND Ground 43 D3 SCSI data bus bit 3 10 GND Ground 44 D4 SCSI data bus bit 4 11 GND Ground 45 D5 SCSI data bus bit 5 12 GND Ground 46 D6 SCSI data bus bit 6 13 GND Ground 47 D7 SCSI data bus bit 7 14 GND Ground 48 DPL SCSI data parity 15 GND Ground 49 GND Ground 16 GND Ground 50 GND Ground 17 TERMPWR Term...

Page 54: ...4 IO Input output 31 GND Ground 65 D8 SCSI data bus bit 8 32 GND Ground 66 D9 SCSI data bus bit 9 33 GND Ground 67 D10 SCSI data bus bit 10 34 GND Ground 68 D11 SCSI data bus bit 11 Table 3 18 68 pin SCSI 3 connector pin assignments Continued Pin Number Signal Mnemonic Signal Name Pin Number Signal Mnemonic Signal Description ...

Page 55: ...E Blue signal 4 NC Not connected 5 DACVSS Video return 6 DACVSS Video return 7 DACVSS Video return 8 DACVSS Video return 9 NC Not connected 10 DACVSS Video return 11 NC Not connected 12 DDCDAT Display data channel data signal for DDC2 support 13 HSYNC Horizontal synchronization 14 VSYNC Vertical synchronization 15 DDCCLK Display data channel clock signal for DDC2 support ...

Page 56: ...Connectors and Components on the CPV5000 3 28 3 Reset switch Table 3 20 Reset switch pin assignments Pin Number Signal Mnemonic 1 Ground 2 FR RSET ...

Page 57: ...ocal bus is a high performance 32 bit bus with multiplexed address and data lines It is intended for use as an interconnect mechanism between highly integrated peripheral controller components peripheral add in boards and processor memory systems The CPV5000 supports a 32 bit PCI interface on the physical CompactPCI connector On board devices connect directly to the primary bus Off board access is...

Page 58: ...CI components Device Name Manufacturer Part Device ID Vendor ID BIOS Extension Host Bridge TXC Intel 82439HX 0x1250 0x8086 N A ISA Bridge PIIX3 Intel 82371 0x7000 0x8086 N A Ethernet Intel 82557 0x1229 0x8086 No SVGA Video Cirrus Logic CL GD5446 0x00B8 0x1013 Yes SCSI Adaptec AIC 7880 0x8078 0x9004 Yes Bridge 1 Digital 21150 0x0022 0x1011 N A ...

Page 59: ...irect access to main memory Watchdog timer The watchdog timer supports four modes of operation Disabled Table 4 2 PCI interrupt routing Description Bus IDSel Device Req Gnt INTA INTB INTC INTD Host Bridge 0 0x00 N A PIIX3 0 AD18 0x07 PHOLD Ethernet 0 AD31 0x14 0 PIRQB Video 0 AD30 0x13 PIRQC Bridge 1 0 AD29 0x12 1 SCSI 0 AD28 0x11 2 PIRQD Slot 1 1 AD31 0x0F 1 0 PIRQD PIRQA PIRQB PIRQC Slot 2 1 AD3...

Page 60: ...he timer supports a range of count down time outs from 18 milliseconds to 291 seconds I O address map PCI system memory and I O are configured or enumerated dynamically each time the system boots or by an operating system Plug and Play but there are legacy I O locations that remain constant Table 4 3 shows I O addressing Functions listed with opt are not normally occupied by on board resources BIO...

Page 61: ...ntroller 2 00C0 00DF DMA controller 2 00F0 Reset coprocessor 0170 01772 Secondary IDE channel opt 01F0 01F72 Primary IDE channel 0278 027F3 Parallel port 2 opt 02E8 02EF3 Serial port 4 opt 02F8 02FF2 Serial port 2 default 0376 03772 Secondary IDE port opt 0378 037F2 Parallel port 1 default 03BC 03C33 Parallel port 3 opt 03E8 03EF3 Serial port 3 opt 03F0 03F5 Floppy channel 03F6 03F7 Primary IDE an...

Page 62: ...operating system Plug and Play but there are legacy memory locations that remain constant Refer to Table 4 4 for memory address information 0678 067A3 Parallel port 2 opt 0778 077A3 Parallel port 1 opt 07BC 07BE3 Parallel port 3 opt 0CF8 0Cff PCI configuration Table 4 4 Memory address Address Range Function 000000H 09FFFFH 640 KB conventional RAM 0A0000H 0BFFFFH VGA DRAM typically on the PCI backp...

Page 63: ... Hz 00 01 16 256 40x25 9x16 360x400 Text 14 31 5 70 02 03 16 256 80x25 9x16 720x400 Text 28 31 5 70 04 05 4 256 40x25 8x8 320x200 Graphics 12 5 31 5 70 6 2 256 80x25 8x8 640x200 Graphics 25 31 5 70 7 mono 80x25 9x16 720x400 Text 28 31 5 70 0D 16 256 40x25 8x8 320x200 Graphics 12 5 31 5 70 0E 16 256 80x25 8x8 640x200 Graphics 25 31 5 70 0F mono 80x25 8x14 640x350 Graphics 25 31 5 70 10 16 256 80x25...

Page 64: ...104 16 256K 128x48 8x16 1024x768 Graphics 65 48 3 60 5D 104 16 256K 128x48 8x16 1024x768 Graphics 75 56 70 5D 104 16 256K 128x48 8x16 1024x768 Graphics 77 58 72 5D 104 16 256K 128x48 8x16 1024x768 Graphics 78 7 60 75 5E 100 256 256K 80x25 8x16 640x400 Graphics 25 31 5 70 5F 101 256 256K 80x30 8x16 640x480 Graphics 25 31 5 60 5F 101 256 256K 80x30 8x16 640x480 Graphics 31 5 37 9 72 5F 101 256 256K ...

Page 65: ... 43 4 68 116 32K 3 1024x768 Graphics 65 48 3 60 68 116 32K 3 1024x768 Graphics 75 56 70 68 116 32K 3 1024x768 Graphics 78 7 60 75 69i 32K 3 1280x1024 Graphics 75 48 43 4 8 6Ci 106 16 256K 160x64 8x16 1280x1024 Graphics 75 48 43 4 8 6Di 107 256 256K 160x64 8x16 1280x1024 Graphics 75 48 43 4 8 6D 107 256 256K 160x64 8x16 1280x1024 Graphics 108 65 60 8 6D 107 256 256K 160x64 8x16 1280x1024 Graphics 1...

Page 66: ...ed using a middle and bottom line algorithm to avoid truncation of descenders For compatibility with some DOS applications which use the 8x14 font the TSRFONT utility should be used 8 VESA has recently proposed a new specification for 43 Hz interlaced and 60 Hz timing for 1280x1024 resolution modes Cirrus Logic currently uses timings for these modes that differ from those proposed by VESA ...

Page 67: ...Ultra SCSI circuitry provides for automatic termination when a device is plugged into the rear or front Devices can be connected to the rear the front or both at the same time Ground pins on the SCSI connector are reassigned to act as cable or device detects Two ground pins are used to distinguish between 16 bit or 8 bit devices The active terminator used is a Dallas Semiconductor DS2105Z This par...

Page 68: ...mination DS2105Z Termination WCD PD 68 Pin SCSI CD 50 PD PD DS2105Z Termination DS2105Z Termination DS2105Z Termination PD PD PD AIC7880 E5 J4 TMD J4 DS2105Z Termination DS2105Z Termination DS2105Z Termination PD PD PD WCD 68 Pin SCSI CD SCD8 15 SCD0 7 CTRL E5 2164 9803 1 1 CPV5000 CPV5000 Transition Module 50 ...

Page 69: ... a wide device must be connected at the end of the cable If a rear I O transition module is plugged in pin E5 will be grounded This will disable the CPV5000 s terminators next to J4 since the end of the SCSI bus will be at the 68 pin connector on the rear I O board If a non wide device is plugged into the rear I O s 68 pin connector pin 50 will become grounded This will cause the terminators for t...

Page 70: ... board IDE hard drive is used it will be connected to the primary IDE port If this is the case only one drive can be connected to the primary rear I O EIDE port and the drive must be jumpered different master or slave than the on board drive Table 4 7 shows all possible on board drive options Floppy interface The floppy interface supports up to two floppy drives The supported floppy drives include...

Page 71: ...tor on the front panel Serial ports The CPV5000 supports two serial ports The ports support 16550 operation The serial interface connector is a 9 pin D style connector available on the rear I O transition module or 9 pin micro D connectors available on the front panel The serial ports are ESD protected to 15KV USB The CPV5000 supports two USB ports with transfer capability from 1 2Mbits second to ...

Page 72: ...r 10 100MB Ethernet The user can enable or disable this feature through the BIOS Setup screen Ethernet connection is available on the front panel or rear I O transition module via a RJ45 connector Front or rear connections are selectable using a four position jumper block Both link and activity LED s are incorporated into the connector in order to indicate network status DMA channels Table 4 8 DMA...

Page 73: ...gement 0 System timer 1 Keyboard 2 Cascade for IRQ 8 15 3 COM 2 serial port 2 4 COM 1 serial port 1 5 Parallel port 2 6 Floppy controller 7 Parallel port 1 8 Real time clock 9 Software redirect to IRQ2 10 Reserved 11 Reserved special features 12 Reserved PS 2 mouse 13 Coprocessor 14 Hard disk controller 15 Reserved ...

Page 74: ...tchdog timer and ENUM registers are accessed via three I O offsets 0Bh 0Dh and 0Fh The LM78 is accessed through port offsets 00h to 07h The following sections describe the function of these registers Port offset 0Bh board status and watchdog strobe An ISA write to I O offset 0Bh will reset the watchdog timer to the value of the watchdog delay programmed into the watchdog register Bit 2 the watchdo...

Page 75: ...d at reset and is selected after any output to the FPGA data port offset 0Fh This last feature helps to protect registers that control important board operations Table 4 12 FPGA register index port Bit 7 6 5 4 3 2 1 0 Function Not used FPGA register index Table 4 13 FPGA register index Index bits 2 0 Index Function 0000 Reserved 0001 Reserved 0010 Reserved 0011 Watchdog index 0100 Reserved 0101 Re...

Page 76: ...locked out mode Watchdog index mode When the timer is enabled the watchdog strobe register must be written to at regular intervals to stop the watchdog from triggering The exact data that is written is irrelevant It is the write operation to the register that resets the watchdog timer The watchdog has four modes when triggered 1 Disabled 2 Set the WD bit in the watchdog strobe register 073h 3 Item...

Page 77: ...hdog bit This bit at logic 1 will clear the watchdog timer function This bit has to be written with a 0 to start the watchdog timer When the watchdog flag in the I O Port offset 0Bh Read is set the flag can only be reset by a write of a 1 to this register Bits 4 3 watchdog mode These two bits control the mode of the watchdog timer Table 4 15 Watchdog register Bit 7 6 5 4 3 2 1 0 Function Clear wat...

Page 78: ... of the interrupt ENUM status and control The level of the ENUM line can be read at bit 0 of this register Bits 1 2 and 3 are read write and can be used to store control bits The control bits are not defined for any particular purpose at this time Table 4 17 Watchdog timer delay Data Watchdog count down delay 000 17 8 milliseconds 001 71 1 milliseconds 010 284 milliseconds 011 1 14 seconds 100 4 5...

Page 79: ...register FPGA index 12h The ENUM storage register is used to store a byte of information for hot swap enabled systems A byte of information can be stored and read back at this location Table 4 19 ENUM Storage Bit 7 6 5 4 3 2 1 0 Function Read write byte storage ...

Page 80: ...Functional Description 4 24 4 ...

Page 81: ...econdary cache EDO memory is available in a x32 SIMM and is non parity EDO and FPM cannot be combined in the same bank The BIOS automatically detects the memory size and type With FPM memory parity generation checking is provided for each byte Additionally the chip set provides single bit Error Checking and Correction ECC and double bit detection Five SIMM sizes 1 MB 2 MB 4 MB 8 MB 16 MB and 32 MB...

Page 82: ...B 2M X 36 8 MB 8M X 36 32 MB 144 MB 2M X 36 8 MB 16M X 36 64 MB 32 MB 4M X 36 16 MB EMPTY 40 MB 4M X 36 16 MB 1M X 36 4 MB 48 MB 4M X 36 16 MB 2M X 36 8 MB 64 MB 4M X 36 16 MB 4M X 36 16 MB 96 MB 4M X 36 16 MB 8M X 36 32 MB 160 MB 4M X 36 16 MB 16M X 36 64 MB 64 MB 8M X 36 32 MB EMPTY 72 MB 8M X 36 32 MB 1M X 36 4 MB 80 MB 8M X 36 32 MB 2M X 36 8 MB 96 MB 8M X 36 32 MB 4M X 36 16 MB 128 MB 8M X 36...

Page 83: ...to static discharge While out of the chassis components should be placed on a static dissipative surface or into a static shielding bag Installation instructions No tools are required for this procedure 1 Remove power from the chassis and disconnect all power cords Remove the CPV5000 from the chassis 2 Locate the SIMM slots on the CPV5000 Hold the SIMM so the notched edge is aligned with the notch...

Page 84: ... sink by disconnecting the cable and then releasing the retaining clip 4 Release the ZIF lever by first pushing the lever away from the socket and then lifting up Lift the processor from the socket Insert the replacement CPU making sure pin 1 on the CPU lines up with pin 1 on the socket 5 After checking that the CPU is fully seated in the socket push the lever down until it locks in place 6 Set th...

Page 85: ...the CPU speed jumper settings 10 Install the CPV5000 in the chassis and connect the power cords Table 5 2 CPU speed settings CPU Speed J10 J15 J14 J29 166 Mhz 2 3 1 2 1 2 2 3 200 Mhz 2 3 2 3 1 2 2 3 233 Mhz 2 3 2 3 2 3 2 3 266 Mhz 2 3 1 2 2 3 1 2 300 Mhz 2 3 1 2 1 2 1 2 2169 9803 ...

Page 86: ...igure on page 3 2 3 Remove the existing battery by lifting up on the battery s edges and sliding it out of the holder Do not try to lift up on the spring clip The clip is there to hold the battery in place it does not function as a release clip 4 Insert the new battery into the holder Note Ensure that you insert the battery with the plus sign facing upwards 5 Install the CPV5000 in the chassis and...

Page 87: ...e Installation instructions Use the following procedure to install the on board disk and floppy drives A number one Phillips screwdriver is needed for this procedure 1 Remove power from the chassis and disconnect all power cords Remove the CPV5000 from the chassis 2 Locate the drive headers on the CPV5000 2167 9803 J6 J9 J8 J7 J12 IDE FLOPPY ...

Page 88: ...e side goes toward the backplane connectors 3 If installing a floppy drive attach one end of the cable to its connector on the CPV5000 To attach the cable push up on each end of the plastic connector The connector releases so that the cable can be inserted in the connector Insert the cable into the connector and push down on each end Attach the other end of the cable in step 7 2170 9803 ...

Page 89: ...ive in the drive carrier Attach the floppy drive to the carrier with two screws on each side 5 If you are installing a hard drive attach the cable to the drive and the IDE connector on the CPV5000 6 Attach the drive carrier to the CPV5000 using two screws 2173 9803 ...

Page 90: ...7 Attach the remaining end of the floppy cable Push up on the tabs on the connector and insert the floppy cable Push down on the tabs to secure the cable 8 Install the CPV5000 in the chassis and connect the power cords 2171 9803 ...

Page 91: ...ides all IBM standard Power On Self Test POST routines as well as enhanced AMIBIOS POST routines AMIBIOS POST supports CPU internal diagnostics POST phases When the system is powered on AMIBIOS executes two types of POST routines The two types of POST routines are System test and initialization tests and initializes AMIBIOS for normal operations System configuration verification compares the defin...

Page 92: ...IOS displayed error messages Refer to Table 6 3 for AMIBIOS displayed error message information Table 6 1 BIOS error reporting If Then The error occurs before the display device is initialized A series of beeps sound Beep codes indicate that a fatal error has occurred AMIBIOS beep codes are described in Table 6 2 The error occurs after the display device is initialized The error message is display...

Page 93: ...re Memory failure in first 64 KB 4 Timer Not Operational A memory failure in the first 64 KB of memory or Timer 1 is not functioning 5 Processor Error The CPU generated an error 6 8042 Gate A20 Failure Cannot switch to protected mode 7 Processor Exception Interrupt Error The CPU on the CPU board generated an exception interrupt 8 Display Memory Read Write Error The system video adapter is either m...

Page 94: ...Table 6 3 AMIBIOS error messages Message Explanation 8042 Gate A20 error Gate A20 on the keyboard controller 8042 is not working Replace the 8042 Address line short Error in the address decoding circuitry C drive error No response from drive C Run the AMIDiag hard disk utility Check the C hard disk type in Standard Setup C drive failure No response from hard disk drive C Replace the drive Cache me...

Page 95: ...r Error in the first DMA channel DMA 2 error Error in the second DMA channel FDD controller failure AMIBIOS cannot communicate with the floppy disk drive controller Check all appropriate connections after the system is powered down HDD controller Failure AMIBIOS cannot communicate with the hard disk drive controller Check all appropriate connections after the system is powered down INTR1 error Int...

Page 96: ... XXXX is the hex address where the error occurred Run AMIDiag to find and correct memory problems On board parity error Parity error in CPV5000 DRAM memory The format is ON BOARD PARITY ERROR ADDR XXXX XXXX is the hex address where the error occurred Run AMIDiag to find and correct memory problems Parity error Parity error in system memory at an unknown address Run AMIDiag to find and correct memo...

Page 97: ...pletes the following message appears Hit DEL if you want to run SETUP Press Del to access WINBIOS Setup ISA NMI handler messages Refer to Table 6 4 for ISA NMI Handler messages Table 6 4 ISA NMI handler messages ISA NMI Message Explanation Memory parity error at xxxxx Memory failed If the memory location can be determined it is displayed as xxxxx If not the message is memory parity error I O board...

Page 98: ...uration screen When the POST routines complete successfully AMIBIOS displays a screen similar to the following AMIBIOS System Configuration C Copyright 1985 95 American Megatrends Inc Main Processor Pentium Base Memory Size 640 KB Numeric Coprocessor Present Ext Memory Size 7808 KB Floppy Drive A 1 2 MB _ Display Type EGA VGA Floppy Drive B 1 44 MB _ Serial Port s 3F8 ROM BIOS Date 07 15 95 Parall...

Page 99: ...Power on delay is starting Next the initialization code checksum will be verified D1h Initializing the DMA controller performing the keyboard controller BAT test starting memory refresh and entering 4 GB flat mode next D3h Starting memory sizing next D4h Returning to real mode Executing any OEM patches and setting the stack next D5h Passing control to the uncompressed code in shadow RAM at E000 00...

Page 100: ...eyboard controller BAT command test 0Fh The initialization after the keyboard controller BAT command test is carried out The keyboard command byte is written next 10h The keyboard controller command byte is written Next issuing the pin 23 and 24 blocking and unblocking commands 11h Next checking if the End or Ins keys were pressed during power on Initializing CMOS RAM if the initialize CMOS RAM in...

Page 101: ...control 2Eh Completed post video ROM test processing If the EGA VGA controller is not found performing the display memory read write test next 2Fh The EGA VGA controller was not found The display memory read write test is about to begin 30h The display memory read write test passed Look for retrace checking next 31h The display memory read write test or retrace checking failed Performing the alter...

Page 102: ...mount of memory above 1 MB was found and verified Checking for a soft reset and clearing the memory below 1 MB for the soft reset next If this is a power on situation going to checkpoint 4Eh next 4Ch The memory below 1 MB was cleared via a soft reset Clearing the memory above 1 MB next 4Dh The memory above 1 MB was cleared via a soft reset Saving the memory size next Going to checkpoint 52h next 4...

Page 103: ...troller 2 base register test passed Programming DMA controllers 1 and 2 next 66h Completed programming DMA controllers 1 and 2 Initializing the 8259 interrupt controller next 7Fh Extended NMI source enabling is in progress 80h The keyboard test has started Clearing the output buffer and checking for stuck keys Issuing the keyboard reset command next 81h A keyboard reset error or stuck key was foun...

Page 104: ...y drive controller next 91h The floppy drive controller was configured Configuring the hard disk drive controller next 95h Initializing the bus option ROMs from C800 next See Table 6 7 for additional information 96h Initializing before passing control to the adaptor ROM at C800 97h Initialization before the C800 adaptor ROM gains control has completed The adaptor ROM check is next 98h The adaptor ...

Page 105: ... the screen and enabling parity and the NMI next A7h NMI and parity enabled Performing any initialization required before passing control to the adaptor ROM at E000 next A8h Initialization before passing control to the adaptor ROM at E000h completed Passing control to the adaptor ROM at E000h next A9h Returned from adaptor ROM at E000h control Performing any initialization required after the E000 ...

Page 106: ...ode Description 2Ah Initializing the different bus system static and output devices if present 38h Initialized bus input IPL and general devices if present 39h Displaying bus initialization error messages if any 95h Initializing bus adaptor ROMs from C8000h through D8000h ...

Page 107: ... Table 6 8 for additional bus checkpoint information Table 6 8 Additional bus checkpoints Bits Description Bits 7 to 4 0000 0001 0010 0011 0100 0101 0110 0111 Function 0 Disable all devices on the bus Function 1 Initialize static devices on the bus Function 2 Initialize output devices on the bus Function 3 Initialize input devices on the bus Function 4 Initialize IPL devices on the bus Function 5 ...

Page 108: ...Power On Self Tests 6 18 6 ...

Page 109: ...ed the DEL key may have to be pressed before the VGA has initialized WinBIOS Setup features This section describes the WinBIOS Setup features Icon based user interface WinBIOS Setup functions are all available in an easily accessible graphical user interface Automatic option selection AMIBIOS can be configured to reflect dependencies between AMIBIOS features and WinBIOS Setup options For example t...

Page 110: ...rt options in Peripheral Setup can be set to 2F8h 3F8h 2E8h or 3E8h If 2F8h is chosen by the end user for Serial Port 1 AMIBIOS disables 2F8h for Serial Port 2 Invalid options are grayed and cannot be selected Point and click interface WinBIOS Setup uses the familiar point and click navigation technique The end user can point with the mouse anywhere on the screen click the left mouse button and Wi...

Page 111: ...st to disable the ticking sound and bypass the memory test The memory click test will only be heard when the Quick boot is disabled Using a mouse with WinBIOS Setup WinBIOS Setup can be accessed via keyboard mouse or pen The mouse click functions are as follows Single click to change or select both global and current fields Double click to perform an operation in the selected field ...

Page 112: ...e right left above or below Enter Select in the current field Increments a value Decrements a value Esc Closes the current operation and return to previous level PgUp Returns to the previous page PgDn Advances to the next page Home Returns to the beginning of the text End Advances to the end of the text Alt H Access a help window Alt Spacebar Exit WinBIOS Setup Alphabetic keys A to Z are used in t...

Page 113: ...tup main menu Windows Function Setup Setup is described starting on page 7 6 This section has Six icons that permits you to set system configuration options such as date time hard disk type floppy type and many others Utilities Utilities is described beginning on page 7 26 Utilities has two icons that perform system functions Security Security is described beginning on page 7 27 Security has three...

Page 114: ...splayed Enter new values through the displayed window Floppy drive A and B Choose the floppy drive A or B icon to specify the floppy drive type The settings are 360 KB 5 25 inch 1 2 MB 5 25 inch 720 KB 3 5 inch 1 44 MB 3 5 inch or 2 88 MB 3 5 inch Table 7 3 WinBIOS Setup Type Description Turn to Standard Setup Set the time and date Configure disk drives 7 6 Advanced Setup Configure basic system pe...

Page 115: ...guring an MFM drive If configuring an MFM hard disk drive you must know the drive parameters number of heads number of cylinders number of sectors the starting write precompensation cylinder and drive capacity Choose Type and choose the appropriate hard disk drive type 1 46 See Table 7 6 for a list of the old MFM hard drive types If the drive parameters of your MFM drive do not match any drive typ...

Page 116: ...k drive Heads Number of heads Write Precompensation The size of a sector gets progressively smaller as the track diameter diminishes Yet each sector must still hold 512 bytes Write precompensation circuitry on the hard disk compensates for the physical difference in sector size by boosting the write current for sectors on inner tracks This parameter is the track number where write precompensation ...

Page 117: ... mode set depends on the operating system in use Refer to Table 7 5 for LBA mode information Click on Block Mode and choose On to support IDE drives that use block mode Click on 32 Bit Mode and click On to support IDE drives that permit 32 bit accesses Table 7 5 LBA mode Operating System Necessary Action SCO UNIX 3 2 4 LBA mode must be disabled in WINBIOS Setup Novell NetWare LBA mode must be disa...

Page 118: ...ose the Type parameter and select CDROM You can boot the computer from a CD ROM drive You can also choose Auto and let AMIBIOS automatically set the correct drive parameters Hard disk drive type Refer to Table 7 6 for hard disk drive type information Table 7 6 Hard drive type information Type Cylinders Heads Write Landing Zone Sector Capacity 1 306 4 128 305 17 10 MB 2 615 4 300 615 17 20 MB 3 615...

Page 119: ... 754 17 69 MB 28 699 7 256 699 17 41 MB 29 823 10 65535 823 17 68 MB 30 918 7 918 918 17 53 MB 31 1024 11 65535 1024 17 94 MB 32 1024 15 65535 1024 17 128 MB 33 1024 5 1024 1024 17 43 MB 34 612 2 128 612 17 10 MB 35 1024 9 65535 1024 17 77 MB 36 1024 8 512 1024 17 68 MB 37 615 8 128 615 17 41 MB 38 987 3 987 987 17 25 MB 39 987 7 987 987 17 57 MB 40 820 6 820 820 17 41 MB 41 977 5 977 977 17 41 MB...

Page 120: ...s up to 40 seconds for a READY signal from the IDE hard disk drive AMIBIOS waits for 0 5 seconds after sending a RESET signal to the IDE drive to allow the IDE drive time to get ready again AMIBIOS checks for a Del key press and runs WINBIOS Setup if the key has been pressed Enabled AMIBIOS does not test system memory above 1 MB AMIBIOS does not wait up to 40 seconds for a READY signal from the ID...

Page 121: ... Num Lock key off when the computer is booted This enables you to use the arrow keys on both the numeric keypad and the keyboard The settings are On or Off Floppy drive swap Set this option to Enabled to permit drives A and B to be swapped The settings are Enabled or Disabled Floppy drive seek Set this option to Enabled to specify that floppy drive A will perform a seek operation at system boot Mo...

Page 122: ...rnal cache settings External cache This option specifies the caching algorithm used for L2 secondary external cache memory Refer to Table 7 9 for a description of external cache settings Table 7 8 Internal cache Setting Description Disabled Neither L1 internal cache memory on the CPU or L2 secondary cache memory is enabled WriteBack default Enable and Use the write back caching algorithm for the o...

Page 123: ...s control the location of the contents of the 16KB of ROM beginning at the specified memory location If no adaptor ROM uses the named ROM area this area is made available to the local bus For more information refer to Table 7 10 which shows an example for C000 16K shadow Table 7 10 System BIOS shadow cacheable Setting Description Shadow The contents of C0000h C3FFFh are written to the same address...

Page 124: ...led or Enabled DRAM speed Specify the RAS access speed of the SIMMs installed in the CPV5000 as system memory The settings are 60 ns or 70 ns The default is 70 ns Manual setting is not supported Note If you have installed SIMMS with different speeds in the CPV5000 select the speed of the slowest SIMM You must always use SIMMS that have the same speed within a memory bank Refresh rate This option i...

Page 125: ...wo clock cycles Leadoff timing This option is only available in manual DRAM setup There are four parameters that are set by this option Read Leadoff timing Write leadoff timing RAS pre charge and Refresh RAS assertion There are four options 7 6 3 4 6 5 3 4 7 6 4 5 and 6 5 4 5 Speculative readoff This option is only available in manual DRAM setup The option when enabled can improve leadoff performa...

Page 126: ... ECC mode can detect and correct a single bit error detect double bit errors and detect all errors confined to a single nibble When this mode is enabled all DRAM leadoff latencies are increased by one cycle DRAM data integrity mode The DRAM data integrity mode has three options Disable When this option is enabled no checks are performed for parity or ECC Parity This option enables byte level parit...

Page 127: ...d in this section Power management Set this option to Enabled to enable the power management and Advanced Power Management APM features The settings are Enabled or Disabled Instant on support Set this option to Enabled to allow the computer to go to full power on mode when leaving a power conserving state This option is only available if supported by external computer hardware AMIBIOS uses the RTC...

Page 128: ...pecified in the Hard Disk Power Down Mode option The settings are Disabled 1 Minute and all one minute intervals up to and including 15 Minutes Full on to standby timeout This option specifies the length of the period of system inactivity when the computer is in Full On mode before the computer is placed in Standby mode In Standby mode some power use is curtailed The settings are Disabled 1 Minute...

Page 129: ...or power conservation purposes When this option is set to Monitor and there is no display activity for the length of time specified by the value in the Full On to Standby Timeout Minute option the computer enters a power saving state The settings are Monitor or Ignore Enabling event monitoring These options enable event monitoring When the computer is in a power saving mode activity on the named i...

Page 130: ...latency of all PCI devices on the PCI bus The settings are in units equal to PCI clocks The settings are 32 64 96 128 160 192 224 or 248 PCI VGA palette snoop This option must be set to Enabled if any ISA adapter board installed in the computer requires VGA palette snooping The settings are Disabled or Enabled PCI IDE bus master Set this option to Enabled to specify that the IDE controller on the ...

Page 131: ...y IRQs for use by legacy ISA adapter boards These options determine if AMIBIOS should remove an IRQ from the pool of available IRQs passed to BIOS configurable devices The available IRQ pool is determined by reading the ESCD NVRAM If more IRQs must be removed from the pool the end user can use these PCI PnP Setup options to remove the IRQ by assigning the option to the ISA EISA setting Onboard I O...

Page 132: ...4000 C8000 CC000 D0000 D4000 D8000 or DC000 This address must be set if the reserved memory size is enabled Peripheral setup Peripheral setup options are displayed by choosing the peripheral setup icon from the WINBIOS Setup main menu All peripheral setup options are described in this section Onboard FDC This option enables the floppy drive controller on the CPV5000 The settings are Auto Enabled o...

Page 133: ...el port DMA This option is only available if the setting for the Parallel Port Mode option is ECP The settings are Disabled DMA CH channel 0 DMA CH 1 or DMA CH 3 Table 7 11 Parallel port mode Setting Description Normal The normal parallel port mode is used This is the default setting Bi Dir Use this setting to support bidirectional transfers on the parallel port EPP The parallel port can be used w...

Page 134: ...These icons are Detect IDE Language Detect IDE This is an option to detect the characteristics of the IDE disks connected to the primary and secondary IDE connectors The auto detection will only operate if the IDE ports are enabled in the peripheral menu under the option of onboard IDE When the IDE disks are detected they are set as USER defined Language English is the only language supported by t...

Page 135: ...evels of passwords The system can be configured so that all users must enter a password every time the system boots or when WINBIOS Setup is executed using either the supervisor password or user password Both passwords have the same level of access to make changes to the system settings If the supervisor password is used to enter the BIOS screens the user password can be changed or deleted without...

Page 136: ... password Select the appropriate password icon Supervisor or User from the Security section of the WINBIOS Setup main menu Type the password and press Enter The screen does not display the characters entered After the new password is entered retype the new password as prompted and press Enter If the password confirmation is incorrect an error message appears If the new password is entered without ...

Page 137: ...ote You may have to type N several times to prevent the boot sector write A typical operating system installation will write to the boot sector of the hard disk drive It is recommended that this option not be enabled during operating system installation Boot Sector Write Possible VIRUS Continue Y N The following message appears after any attempt to format any cylinder head or sector of any hard di...

Page 138: ...INBIOS Setup when you first began this WINBIOS Setup session Optimal You can load the optimal default settings for the WINBIOS by selecting the Optimal icon The Optimal default settings are best case values that should optimize system performance If CMOS RAM is corrupted the Optimal settings should be loaded Fail Safe You can load the Fail Safe WINBIOS Setup option settings by selecting the Fail S...

Page 139: ...codes BIOS 6 15 C cache memory WinBIOS setup 7 14 CD ROM drive WinBIOS setup 7 10 checklist installation 2 2 checkpoint codes bus 6 15 POST 6 9 runtime 6 10 chip functions 3 1 chipset setup WinBIOS setup 7 16 codes BIOS beeps 6 3 COM1 and COM2 pin assignments 3 22 CompactPCI user I O connectors 3 8 components location 3 2 components and connectors 3 1 configuration screen BIOS 6 8 configuring head...

Page 140: ...nments 3 19 floppy drive installation 5 7 floppy drives supported 4 14 floppy interface 4 14 FPGA access registers 4 18 FPM memory 5 1 front panel diagram 2 6 I O interfaces 1 3 front panel connectors 3 6 H hard disk drives EIDE connectors 3 17 hard disk types WinBIOS setup 7 10 headers configuring 3 3 I I O address map 4 4 I O addresses 4 5 I O interfaces 1 3 ID codes PCI components 4 2 IDE drive...

Page 141: ... PCI host bridge chip 3 1 PCI interrupt routing 4 3 PCI local bus 4 1 PCI system memory 4 4 PCI PnP WinBIOS setup 7 22 PCI ISA bridge chip 3 1 PCI PCI bridge chip 3 1 peripheral setup WinBIOS setup 7 24 PICMG 1 1 POST checkpoint codes 6 9 POST memory test 6 7 POST phases 6 1 power management WinBIOS setup 7 19 power on tests BIOS 6 1 power up procedures 2 5 processor upgrade installation 5 4 progr...

Page 142: ...chip 3 1 ultra SCSI controller 4 11 uncompressed initialization codes BIOS 6 9 USB configuration 3 6 USB ports 4 15 USB ports pin assignments 3 23 utility menu WinBIOS setup 7 26 V video chip 3 1 video connector pin assignments 3 27 video controller 4 7 video modes extended 4 8 standard 4 7 virus protection WINBIOS setup 7 29 W watchdog index mode 4 20 watchdog registers 4 18 watchdog strobe 4 18 ...

Page 143: ...I Single Board Computer Installation and Reference Guide CPX5000A IH3 34 pages 1 8 spine 36 84 pages 3 16 1 4 spine 86 100 pages 5 16 spine 102 180 pages 3 8 1 2 spine 182 308 pages 5 8 1 1 8 spine 2 lines allowed Cover ...

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