92
Remark
For timer and counter present values, there are no limits on index register numbers used.
(c) A case where Indexing has been performed, and the actual process device, would be as follows:
(When Z0 20 and Z1 -5)
Fig. 3.7 Ladder Example and Actual Process Device
(3) Indexing with 32-bit (Universal model QCPU (excluding Q00UJCPU) and LCPU)
A method of specifing index registers in indexing with 32-bit can be selected from the following two methods.
• Specifing the index registers’ range used for indexing with 32-bit.
• Specifing the 32-bit indexing using “ZZ” specification.
32-bit indexing with the "ZZ" specification is only available for the following CPU modules. See the programming tool
operating manual for the available programming tools.
• The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher. (excluding Q00UJCPU)
• QnUDE(H)CPU
• LCPU
Ladder Example
Actual Process Device
SM
4
00
P
resent
v
alue
o
f timer
X0
Value set f
o
r timer
T
0
K
100
T
0Z
4
K4Y
30
BCD
SM
4
00
P
resent
v
alue
o
f c
o
unter
X1
Value set f
o
r c
o
unter
C100
K
10
C100Z
6
K
2
Y4
0
BCD
X0
MO
V
K20
Z0
MO
V
K
5
Z1
X1
MO
V
K2X
5
0Z0 K1M3
8
Z1
D
escripti
o
n
Co
n
v
erts K
20
int
o
a hexa
d
ecimal number.
X1
MO
V K
2X
64
K
1M33
K
2X
5
0Z0
K
1M3
8
Z1
K
1M(3
8 - 5
)
= K
1M33
K
2X(
5
0
+
1
4
)
= K
2X
64
X0
MO
V
K20
Z0
MO
V
K
Z1
X1
MO
V
D0Z0
K3Y12FZ1
5
D
escripti
o
n
Hexa
d
ecimal number
X1
MO
V
D20
K
3
Y
12A
D0Z0
K
3
Y
12
F
Z1
D
(0
+
20)
=
D20
K
3
Y
(12
F - 5
)
= K
3
Y
12A
