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Table of contents
CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) .............................................. 2
2.1 Accumulator (A) ........................................................................................................................ 2
2.2 Index Register X (X), Index Register Y (Y) ........................................................................ 2
2.3 Stack Pointer (S) ....................................................................................................................... 3
2.4 Program Counter (PC) ............................................................................................................. 4
2.5 Processor Status Register (PS) ............................................................................................. 4
3.1 Addressing Mode ...................................................................................................................... 6
3.2 Instruction Set ......................................................................................................................... 26
3.2.1 Data transfer instructions................................................................................................ 26
3.2.2 Operating instruction ....................................................................................................... 27
3.2.3 Bit managing instructions ...............................................................................................28
3.2.4 Flag setting instructions .................................................................................................. 28
3.2.5 Jump, Branch and Return instructions......................................................................... 28
3.2.6 Interrupt instruction (Break instruction) ........................................................................ 29
3.2.7 Special instructions .......................................................................................................... 29
3.2.8 Other instruction .............................................................................................................. 29
4.1.1 Setting for interrupt request bit and interrupt enable bit......................................... 102
4.1.2 Switching of detection edge ........................................................................................ 102
4.1.3 Distinction of interrupt request bit .............................................................................. 103
4.2.1 Processor Status Register ........................................................................................... 104
4.2.2 BRK instruction .............................................................................................................. 105
4.2.3 Decimal calculations ...................................................................................................... 105
4.2.4 JMP instruction .............................................................................................................. 106
APPENDIX 1. Instruction Cycles in each Addressing Mode ........................ 107
APPENDIX 2. 740 Family Machine Language Instruction Table .................. 173
APPENDIX 3. 740 Family list of Instruction Codes ......................................... 179
Table of contents