Mitsubishi M16C/20 Series Software Manual Download

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TXS

RANSFER INDEX REGISTER

TACK POINTER

(S)

←

(X)

This instruction stores the contents of X in S.

No change

Op e r a t io n :

F u n c t io n :

St a t u s fla g

Cycle number

Byte number

Machine codes

Statement

∆

TXS

Addressing mode

Implied

Summary of Contents for M16C/20 Series

Page 1: ...ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 8 BIT SINGLE CHIP MICROCOMPUTER 740 FAMILY 740 Family MITSUBISHI ELECTRIC Software Manual ...

Page 2: ...nd are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein Mitsubishi Electric Corporation semiconductors are not des...

Page 3: ...Rev Rev No date 1 0 First Edition 970829 REVISION DESCRIPTION LIST 740 Family Software Manual 1 1 Revision Description ...

Page 4: ...ures addressing modes and instructions are introduced in each section The enhanced instruction set with enhanced data and memory operations enable efficient programming Please refer to the USER S MANUAL appropriate for the hardware device or the development support tools used ...

Page 5: ... 6 Interrupt instruction Break instruction 29 3 2 7 Special instructions 29 3 2 8 Other instruction 29 3 3 Description of instructions 30 CHAPTER 4 NOTES ON USE 102 4 1 Notes on interrupts 102 4 1 1 Setting for interrupt request bit and interrupt enable bit 102 4 1 2 Switching of detection edge 102 4 1 3 Distinction of interrupt request bit 103 4 2 Notes on programming 104 4 2 1 Processor Status R...

Page 6: ...e Bit Relative 25 Instructions ADC 31 AND 32 ASL 33 BBC 34 BBS 35 BCC 36 BCS 37 BEQ 38 BIT 39 BMI 40 BNE 41 BPL 42 BRA 43 BRK 44 BVC 45 BVS 46 CLB 47 CLC 48 CLD 49 CLI 50 CLT 51 CLV 52 CMP 53 COM 54 CPX 55 CPY 56 DEC 57 DEX 58 DEY 59 DIV 60 EOR 61 INC 62 INX 63 INY 64 JMP 65 JSR 66 LDA 67 LDM 68 LDX 69 LDY 70 LSR 71 MUL 72 NOP 73 ORA 74 PHA 75 PHP 76 PLA 77 PLP 78 ROL 79 ROR 80 RRF 81 RTI 82 RTS 8...

Page 7: ... test and branch instructions can be performed on the Accu mulator memory or I O area 3 Multiple interrupts with separate interrupt vectors allow servicing of different non periodic events 4 Byte processing and table referencing can be easily performed using the index addressing mode 5 Decimal mode needs no software correction for proper decimal operation 6 The Accumulator does not need to be used...

Page 8: ...ntly for arithmetic operations data transfer temporary memory conditional judgments etc 2 2 Index Register X X Index Register Y Y The 740 Family has an Index Register X and an Index Register Y both of which are eight bit registers When using addressing modes which use these index registers the address which is added the contents of Index Register to the address specified with operand is accessed T...

Page 9: ... the PHA instruction saves the Accumulator contents to an address using the Stack Pointer contents as the low order eight bits of the address The RTI instruction is executed to return from an interrupt routine When the RTI instruction is executed the following procedure is performed automatically in sequence 1 The Stack Pointer contents are incremented by 1 2 The contents of an address using the S...

Page 10: ...flag stores any carry or borrow from the Arithmetic Logic Unit ALU after an arithmetic operation and is also changed by the Shift or Rotate instruction This flag is set by the SEC instruction and is cleared by the CLC instruction Zero flag Z Bit 1 This flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result Interrupt disable flag I Bit 2 This...

Page 11: ...et to 1 when an overflow occurs as a result of a signed arithmetic operation An overflow occurs when the result of an addition or subtraction exceeds 127 7F16 or 128 8016 respectively The CLV instruction clears the Overflow Flag There is no set instruction The overflow flag is also set during the BIT instruction when bit 6 of the value being tested is 1 Overflows do not occur when the result of an...

Page 12: ...de which forms the basis of the instruction The second or third byte is called the oper and which affects the addressing The contents of index registers X and Y can also effect the addressing Although there are many addressing modes there is always a particular memory location specified What differs is whether the operand or the index register contents or a combination of both should be used to sp...

Page 13: ...n s Ex a m p le Immediate Specifies the Operand as the data for the instruction ADC AND CMP CPX CPY EOR LDA LDX LDY ORA SBC Mnemonic Machine code ADC A5 6916 A516 Addressing mode This symbol indicates the Immediate addressing mode AAAAAA AAAAAA Op code 6916 Operand A516 Memory A A C A516 ...

Page 14: ...n g m o d e F u n c tio n In s tru c tio n s Ex a m p le Accumulator Specifies the contents of the Accumulator as the data for the instruction ASL DEC INC LSR ROL ROR Mnemonic Machine code ROL A 2A16 Addressing mode Accumulator C Carry flag bit 7 bit 0 ...

Page 15: ...ation is determined by using Operand as the low order byte of the address and 0016 as the high order byte ADC AND ASL BIT CMP COM CPX CPY DEC EOR INC LDA LDM LDX LDY LSR ORA ROL ROR RRF SBC STA STX STY TST Mnemonic Machine code ADC 40 6516 4016 Addressing mode 4016 0016 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA FF16 A A C XX16 Zero page designation Data XX16 Op c...

Page 16: ... added If as a result of this addition a carry occurs it is ignored b The result of the addition is used as the low order byte of the address and 0016 as the high order byte ADC AND ASL CMP DEC DIV EOR INC LDA LDY LSR MUL ORA ROL ROR SBC STA STY Mnemonic Machine code ADC 5E X 7516 5E16 Addressing mode 4416 0016 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Zero page Data XX16 FF16...

Page 17: ... a Operand and the Index Register Y are added if as a result of this addition a carry occurs it is ig nored b The result of the addition is used as the low order byte of the address and 0016 as the high order byte LDX STX Mnemonic Machine code LDX 62 Y B616 6216 Addressing mode 6816 0016 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Zero page Data XX16 FF16 Op code B616 Operand 62...

Page 18: ... in the memory location is determined by using Operand I as the low order byte of the address and Operand II as the high order byte ADC AND ASL BIT CMP CPX CPY DEC EOR INC JMP JSR LDA LDX LDY LSR ORA ROL ROR SBC STA STX STY Mnemonic Machine code ADC AD12 6D16 1216 AD16 Addressing mode AAAAAA AAAAAA Op code 6D16 Operand I 1216 Operand II AD16 A A C XX16 Data XX16 Memory AD1216 Absolute designation ...

Page 19: ...erand I is used as the low order byte of an address Operand II as the high order byte b Index Register X is added to the address above The result is the address in the memory location ADC AND ASL CMP DEC EOR INC LDA LDY LSR ORA ROL ROR SBC STA Mnemonic Machine code ADC AD12 X 7D16 1216 AD16 Addressing mode EE16 AE0016 AAAAA AAAAA Op code 7D16 Operand I 1216 Operand II AD16 A A C XX16 Data XX16 Mem...

Page 20: ...lowing a Operand I is used as the low order byte of an address Operand II as the high order byte b Index Register Y is added to the address above The result is the address in the memory location ADC AND CMP EOR LDA LDX ORA SBC STA Mnemonics Machine code ADC AD12 Y 7916 1216 AD16 Addressing mode EE16 AE0016 AAAAAA AAAAAA Op code 7916 Operand I 1216 Operand II AD16 A A C XX16 Data XX16 Memory AE0016...

Page 21: ...the Accumulator but the address is always inherent in the instruction BRK CLC CLD CLI CLT CLV DEX DEY INX INY NOP PHA PHP PLA PLP RTI RTS SEC SED SEI SET STP TAX TAY TSX TXA TXS TYA WIT Mnemonic Machine code CLC 1816 IN STRUC TION S Addressing mode Processor status register 0 Carry flag bit 7 bit 0 Carry flag is cleared to 0 ...

Page 22: ... addition is the address in the memory location When the branch condition is not satisfied the next instruction is executed BCC BCS BEQ BMI BNE BPL BRA BVC BVS Mnemonic Machine code BCC 12 9016 F216 Decimal AAAAAA AAAAAA AAAAAA 2 AA AA A A A A AA AA AA AA Address to be executed next Op code 9016 Operand F216 Jump Memory AAAAAA AAAAAA AAAAAA 2 Op code 9016 Operand F216 Memory Address to be executed...

Page 23: ...mory location and 0016 as the high order byte c The contents of the address in the Zero Page memory location is used as the low order byte of the address in the memory location d The next Zero Page memory location is used as the high order byte of the address in the memory location ADC AND CMP EOR LDA ORA SBC STA Mnemonic Machine code ADC 1E X 6116 1E16 Addressing mode AAAAA AAAAA AAAAA AAAAA AAAA...

Page 24: ...e low order byte of an address The next Zero Page memory location is used as the high order byte c The Index Register Y is added to the address in Step b The result of this addition is the address in the memory location ADC AND CMP EOR LDA ORA SBC STA Mnemonic Machine code ADC 1E Y 7116 1E16 Addressing mode AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA A A C XX16 Data XX16 12E716 Op code...

Page 25: ...ontents of the next address as the high order byte c The high order and low order bytes in step b together form the address in the memory location JMP Mnemonic Machine code JMP 1400 6C16 0016 1416 Addressing mode AAAAA AAAAA Op code 6C16 Operand I 0016 Operand II 1416 AAAA A A A A A A A AA AA AA AA AA AA 140016 1EFF16 Jump Data II 1E16 Data I FF16 Address to be executed next Indirect designation M...

Page 26: ...ry location is used as the low order byte and the contents of the next Zero Page memory location as high order byte c The high order and low order bytes in step b together form the address of the memory location JMP JSR Mnemonic Machine code JMP 45 B216 4516 Addressing mode Ze ro Pa g e In d ire c t AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Data II 1E16 Data I FF16 AAAAAA AAAAAA Op code B216 Opera...

Page 27: ... the Special Page memory location is determined by using Operand as the low order byte of the address and FF16 as the high order byte JSR Mnemonic Machine code JSR FFC0 2216 C016 This symbol indicates the Special page mode AAAAA AAAAA AAAAA Op code 2216 Operand C016 AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA FF0016 FFFF16 FFC016 Special page AAA AAA AA AA A A A A Jump Special page desig...

Page 28: ...struction Operand is used as the low order byte of the address in the Zero Page memory location and 0016 as the high order byte The bit position is designated by the high order three bits of the Op code CLB SEB Mnemonic Machine code CLB 5 44 BF16 4416 Addressing mode Memory Zero page FF16 0016 4416 Op code BF16 0 1 1 1 1 1 1 1 bit 5 Bit designation bit 5 4416 Zero page designation Zero page Operan...

Page 29: ...e Accumulator Bit Specifies one bit of the Accumulator as the data for the instruction The bit position is designated by the high order three bits of the Op Code CLB SEB Mnemonic Machine code CLB 5 A BB16 Addressing mode 1 1 1 1 1 1 0 Accumulator bit 5 Memory Accumulator 0 bit 5 0 Op code BB16 Bit designation ...

Page 30: ...nd and the Program Counter are added The result of this addition is the address in the memory location When the branch condition is not satisfied the next instruction is executed BBC BBS Mnemonic Machine code BBC 5 A 12 B316 F216 Decimal 0 1 1 1 1 1 0 Accumulator bit 5 Memory 0 Operand F216 Address to be executed next 12 2 Jump 0 1 1 1 1 1 1 0 Accumulator bit 5 Memory 0 Operand F216 Address to be ...

Page 31: ...ondition is not satisfied the next instruction is executed BBC BBS Mnemonic Machine language BBC 5 04 12 B716 0416 F116 Addressing mode Ze ro Pa g e Bit Re la tiv e Ad d re s s in g m o d e F u n c tio n In s tru c tio n s Ex a m p le Decimal Zero page designation 0 1 1 1 1 1 0 bit 5 Memory 1 Operand I 0416 Address to be executed next 12 0 1 1 1 1 1 0 1 Operand I 0416 3 Address to be executed next...

Page 32: ...d memory contents into Index Register X Load memory contents into Index Register Y Store Accumulator into memory Store Index Register X into memory Store Index Register Y into memory Transfer Accumulator to the Index Register X Transfer Index Register X into the Accumulator Transfer Accumulator into the Index Register Y Transfer Index Register Y into the Accumulator Transfer Stack Pointer into the...

Page 33: ...h Accumulator or memory where is indicated by Index Register X OR memory with Accumulator or memory where is indicated by Index Register X Exclusive OR memory with Accumulator or memory where is indicated by Index Register X Store one s complement of memory contents to memory AND memory with Accumulator The result is not stored into anywhere Test whether memory content is 0 or not Compare memory c...

Page 34: ...ns clear 0 or set 1 designated bits of the Accumulator or memory Instructions CLB SEB Contents Clear designated bit in the Accumulator or memory Set designated bit in the Accumulator or memory Bit Managing C flag Carry Flag Z flag Zero Flag N flag Negative Flag V flag Overflow Flag Instructions JMP BRA JSR BBC BBS BCC BCS BNE BEQ BPL BMI BVC BVS RTI RTS Contents Jump to new location Jump to new lo...

Page 35: ...struction Break instruction This instruction causes a software interrupt 3 2 7 Special instructions These special instructions control the oscillation and the internal clock 3 2 8 Other instruction Special Contents Only advances the program counter Instruction NOP Other Contents Stops the internal clock Stops the oscillation of oscillator ...

Page 36: ...Zero page address data in 0 to 255 Data in 0 to 255 Data in 0 to 7 Contents of the Program Counter Tab or space Immediate mode Special page mode Hexadecimal symbol Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Contents of register memory etc Direction of data transfer Description Accumulator Bit i of Accumulator Program Counter Low order byte of Program C...

Page 37: ...ration result is 0 otherwise it is 0 C is 1 when the result of a binary addition exceeds 255 or when the result of a decimal addition exceeds 99 otherwise it is 0 Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Byte number 2 2 2 3 3 3 2 2 Statement ADC nn ADC zz ADC zz X ADC hhll ADC hhll X ADC hhll Y ADC zz X ADC zz Y Machine codes 6916 nn16 6516 zz16 7516 zz16 6D16 ll16 hh16 7D16 ll16...

Page 38: ...ory where is indicated by X N is 1 when bit 7 is 1 after the operation otherwise it is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise it is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Addressing mode Immediate Zero page Zero page X Absolute Absolute X Absolute Y Indirect X Indirect Y Statement AND nn AND zz AND zz X AN...

Page 39: ...7 of A or M is 1 after the operation otherwise it is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise it is 0 C is 1 when bit 7 of A or M is 1 before this operation otherwise it is 0 Cycle number 2 5 6 6 7 Byte number 1 2 2 3 3 Machine codes 0A16 0616 zz16 1616 zz16 0E16 ll16 hh16 1E16 ll16 hh16 Addressing mode Accumulator Zero page Zero page X Ab...

Page 40: ...nstruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 4 5 Byte number 2 3 Addressing mode Accumulator bit Relative Zero page bit Relative Statement BBC i A hhll BBC i zz hhll Notes 1 rr16 hhll n The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number 3 When executing the BBC instruction after the contents of the interrup...

Page 41: ...instruction is exe cuted No change Op e ra tio n F u n c tio n Sta tu s fla g Machine codes 20i 3 16 rr16 20i 7 16 zz16 rr16 Cycle number 4 5 Byte number 2 3 Addressing mode Accumulator bit Relative Zero page bit Relative Statement BBS i A hhll BBS i zz hhll Notes 1 rr16 hhll n The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number 3 When executing the B...

Page 42: ...ress is specified by a relative address If C is 1 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 2 Addressing mode Relative Machine codes 9016 rr16 Statement BCC hhll Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 43: ...ess is specified by a relative address If C is 0 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Relative Statement BCS hhll Machine codes B016 rr16 Byte number 2 Cycle number 2 Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 44: ...s is specified by a relative address If Z is 0 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Relative Statement BEQ hhll Machine codes F016 rr16 Byte number 2 Cycle number 2 Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 45: ...of A M remain unchanged N is 1 when bit 7 of M is 1 otherwise it is 0 V is 1 when bit 6 of M is 1 otherwise it is 0 No change No change No change No change Z is 1 when the result of the operation is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Cycle number 3 4 Machine codes 2416 zz16 2C16 ll16 hh16 Statement BIT zz BIT hhll Byte number 2 3 Addressing mode...

Page 46: ...dress is specified by a relative address If N is 0 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Statement BMI hhll Addressing mode Relative Machine codes 3016 rr16 Byte number 2 Cycle number 2 Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 47: ...ess is specified by a relative address If Z is 1 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 2 Machine codes D016 rr16 Statement BNE hhll Addressing mode Relative Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 48: ...ess is specified by a relative address If N is 1 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Relative Statement BPL hhll Machine codes 1016 rr16 Byte number 2 Cycle number 2 Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 49: ...ted address The branch address is specified by a relative address No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 4 Byte number 2 Machine codes 8016 rr16 Statement BRA hhll Addressing mode Relative Note rr16 hhll 2 The rr16 is a value in a range of 128 to 127 ...

Page 50: ...016 Byte number 1 Cycle number 7 Notes 1 BADRS means a break address 2 The value of the PC pushed onto the stack by the execution of the BRK instruction is the BRK instruction address plus two Therefore the byte following the BRK will not be executed when the value of the PC is returned from the BRK routine 3 Both after the BRK instruction is executed and after INT is input the program is branched...

Page 51: ...dress is specified by a relative address If V is 1 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Machine codes 5016 rr16 Cycle number 2 Byte number 2 Addressing mode Relative Statement BVC hhll Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 52: ...ress is specified by a relative address When V is 0 the next instruction is executed No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 2 Machine codes 7016 rr16 Statement BVS hhll Addressing mode Relative Notes 1 rr16 hhll 2 The rr16 is a value in a range of 128 to 127 2 When a branch is executed add 2 to the cycle number ...

Page 53: ...struction clears the designated bit i of A or M No change Op e ra tio n F u n c tio n Sta tu s fla g Machine codes 20i 1B 16 20i 1F 16 ZZ16 Byte number 1 2 Cycle number 2 5 Statement CLB i A CLB i zz Addressing mode Accumulator bit Zero page bit ...

Page 54: ...s instruction clears C No change No change No change No change No change No change No change 0 Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Addressing mode Implied Statement CLC Machine codes 1816 Byte number 1 Cycle number 2 ...

Page 55: ...is instruction clears D No change No change No change No change No change 0 No change No change Op e ra tio n F u n c tio n Sta tu s fla g Statement CLD Machine codes D816 Byte number 1 N V T B I D Z C Addressing mode Implied Cycle number 2 ...

Page 56: ...TATUS Addressing mode Implied Statement CLI Machine codes 5816 Byte number 1 Cycle number 2 Operation Function Status flag N V T B I D Z C I 0 This instruction clears I No change No change No change No change 0 No change No change No change ...

Page 57: ...is instruction clears T No change No change 0 No change No change No change No change No change Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Implied Machine codes 1216 Byte number 1 Cycle number 2 Statement CLT N V T B I D Z C ...

Page 58: ...is instruction clears V No change 0 No change No change No change No change No change No change Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Implied Byte number 1 Machine codes B816 Statement CLV N V T B I D Z C Cycle number 2 ...

Page 59: ...ration otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 C is 1 when the subtracted result is equal to or greater than 0 otherwise C is 0 Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 3 4 4 5 5 6 6 Addressing mode Immediate Zero page Zero page X Absolute Absolute X Absolute Y Indirect X Indirect Y Statement CMP nn ...

Page 60: ...hen bit 7 of the M is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Zero page Statement COM zz Machine codes 4416 zz16 Cycle number 5 Byte number 2 N V T B I D Z C ...

Page 61: ...er the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 C is 1 when the subtracted result is equal to or greater than 0 otherwise C is 0 Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Addressing mode Immediate Zero page Absolute Statement CPX nn CPX zz CPX hhll Machine codes E016 nn16 E416 zz16 EC16 ll16...

Page 62: ...er the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 C is 1 when the subtracted result is equal to or greater than 0 otherwise C is 0 Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Addressing mode Immediate Zero page Absolute Machine codes C016 nn16 C416 zz16 CC16 ll16 hh16 Cycle number 2 3 4 Byte num...

Page 63: ...change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Accumulator Zero page Zero page X Absolute Absolute X Machine codes 1A16 C616 zz16 D616 zz16 CE16 ll16 hh16 DE16 ll16 hh16 Cycle number 2 5 6 6 7 Byte number 1 2 2 3 3 Statement DEC A DEC zz DEC zz X DEC hhll DEC hhll X N V T B I D Z C ...

Page 64: ... is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Addressing mode Implied Machine codes CA16 Byte number 1 Cycle number 2 Statement DEX ...

Page 65: ... is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Addressing mode Implied Statement DEY Machine codes 8816 Cycle number 2 Byte number 1 ...

Page 66: ...Statement DIV zz X Machine codes E216 zz16 Byte number 2 Cycle number 16 Notes 1 The quotient s overflow and zero division can not be detected Check the quotient s overflow and zero division by software before DIV instruction is executed This instruction changes the Stack Pointer and the contents of the Accumulator 2 The DIV instruction can not be used for any products Op e ra tio n F u n c tio n ...

Page 67: ... changed M X represents the contents of memory where is indicated by X N is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change N V T B I D Z C Addressing mode Immediate Zero page Zero page X Absolute Absolute X Absolute Y Indirect X Indirect Y Machine codes 4916 nn16 4516 zz16 551...

Page 68: ...INC zz X INC hhll INC hhll X Machine codes 3A16 E616 zz16 F616 zz16 EE16 ll16 hh16 FE16 ll16 hh16 Cycle number 2 5 6 6 7 Byte number 1 2 2 3 3 A A 1 or M M 1 This instruction adds one to the contents of A or M N is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change ...

Page 69: ...ion adds one to the contents of X N is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change N V T B I D Z C Statement INX Machine codes E816 Cycle number 2 Byte number 1 Addressing mode Implied ...

Page 70: ...en bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Cycle number Op e ra tio n F u n c tio n Sta tu s fla g Addressing mode Implied Statement INY Machine codes C816 Byte number 1 2 N V T B I D Z C ...

Page 71: ...ect Absolute then PCL zz PCH zz 1 This instruction jumps to the address designated by the following three addressing modes Absolute Indirect Absolute Zero Page Indirect Absolute No change Cycle number 3 5 4 Byte number 3 3 2 Machine codes 4C16 ll16 hh16 6C16 ll16 hh16 B216 zz16 Statement JMP hhll JMP hhll JMP zz Addressing mode Absolute Indirect Absolute Zero Page Indirect ...

Page 72: ...he stack then jumps to the address designated by the following addressing modes Absolute Special Page Zero Page Indirect Absolute No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 6 5 7 Note 5C16 of the ASCII code denotes special page hh16 must be FF16 in the special page addressing mode Byte number 3 2 2 Machine codes 2016 ll16 hh16 2216 ll16 0216 zz16 Statement JSR hhll JSR hhll ...

Page 73: ...bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change N V T B I D Z C Cycle number 2 3 4 4 5 5 6 6 Byte number 2 2 2 3 3 3 2 2 Machine codes A916 nn16 A516 zz16 B516 zz16 AD16 ll16 hh16 BD16 ll16 hh16 B916 ll16 hh16 A116 zz16 B116 zz16 Statement LDA nn LDA zz LDA zz X LDA hhll LDA hhll X LD...

Page 74: ...TE DATA TO MEMORY M nn This instruction loads the immediate value in M No change Cycle number 4 Byte number 3 Machine codes 3C16 nn16 zz16 Statement LDM nn zz Addressing mode Zero page Op e ra tio n F u n c tio n Sta tu s fla g ...

Page 75: ...ge No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Cycle number 2 3 4 4 5 Byte number 2 2 2 3 3 Machine codes A216 nn16 A616 zz16 B616 zz16 AE16 ll16 hh16 BE16 ll16 hh16 Statement LDX nn LDX zz LDX zz Y LDX hhll LDX hhll Y Addressing mode Immediate Zero page Zero page Y Absolute Absolute Y ...

Page 76: ...ge No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Addressing mode Immediate Zero page Zero page X Absolute Absolute X Statement LDY nn LDY zz LDY zz X LDY hhll LDY hhll X Machine codes A016 nn16 A416 zz16 B416 zz16 AC16 ll16 hh16 BC16 ll16 hh16 Cycle number 2 3 4 4 5 Byte number 2 2 2 3 3 Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C ...

Page 77: ...e operation result is 0 otherwise Z is 0 C is 1 when the bit 0 of either the A or the M before the operation is 1 otherwise C is 0 Op e ra tio n F u n c tio n Sta tu s fla g 0 b7 b0 C N V T B I D Z C Cycle number 2 5 6 6 7 Byte number 1 2 2 3 3 Machine codes 4A16 4616 zz16 5616 zz16 4E16 ll16 hh16 5E16 ll16 hh16 Statement LSR A LSR zz LSR zz X LSR hhll LSR hhll X Addressing mode Accumulator Zero p...

Page 78: ...in A No change M UL M UL MULTIPLY ACCUMULATOR AND MEMORY Op e ra tio n F u n c tio n Sta tu s fla g M zz X M S Zero page multiplicant product multiplier A A Statement MUL zz X Machine codes 6216 zz16 Cycle number 15 Byte number 2 Addressing mode Zero page X Notes 1 This instruction changes the contents of S and A 2 The MUL instruction can not be used for some products high order low order ...

Page 79: ...PERATION Addressing mode Implied Statement NOP PC PC 1 This instruction adds one to the PC but does no other operation No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle Number 2 Byte number 1 Machine codes EA16 ...

Page 80: ... X represents the contents of memory where is indicated by X N is when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the execution result is 0 otherwise Z is 0 No change N V T B I D Z C Cycle number 2 3 4 4 5 5 6 6 Byte number 2 2 2 3 3 3 2 2 Statement ORA nn ORA zz ORA zz X ORA hhll ORA hhll X ORA hhll Y ORA zz X ORA zz Y Addressing ...

Page 81: ... u n c tio n Sta tu s fla g M S A S S 1 This instruction pushes the contents of A to the memory location designated by S and decrements the contents of S by one No change Machine codes 4816 Statement PHA Cycle number 3 Byte number 1 Addressing mode Implied ...

Page 82: ...his instruction pushes the contents of PS to the memory loca tion designated by S and decrements the contents of S by one No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 3 Byte number 1 Machine codes 0816 Statement PHP Addressing mode Implied ...

Page 83: ...nd stores the contents of the memory designated by S in A N is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change N V T B I D Z C Cycle number 4 Byte number 1 Machine codes 6816 Statement PLA Addressing mode Implied ...

Page 84: ...crements S by one and stores the contents of the memory location designated by S in PS Value returns to the original one that was pushed in the stack Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 4 Byte number 1 Machine codes 2816 Statement PLP Addressing mode Implied ...

Page 85: ...e N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 C is 1 when bit 7 is 1 before the operation otherwise C is 0 b7 b0 C Cycle number 2 5 6 6 7 Byte number 1 2 2 3 3 Machine codes 2A16 2616 zz16 3616 zz16 2E16 ll16 hh16 3E16 ll16 hh16 Statement ROL A ROL zz ROL zz X ROL hhll ROL hhll X Addressing mode Accumulator Zero page Zero page X A...

Page 86: ...ange No change Z is 1 when the operation result is 0 otherwise Z is 0 C is 1 when bit 0 is 1 before the operation otherwise C is 0 Op e ra tio n F u n c tio n Sta tu s fla g C b7 b0 Cycle number 2 5 6 6 7 Byte number 1 2 2 3 3 Machine codes 6A16 6616 zz16 7616 zz16 6E16 ll16 hh16 7E16 ll16 hh16 Statement ROR A ROR zz ROR zz X ROR hhll ROR hhll X Addressing mode Accumulator Zero page Zero page X Ab...

Page 87: ...UR BITS Op e ra tio n F u n c tio n Sta tu s fla g b7 b4 b3 b0 This instruction rotates 4 bits of the M content to the right No change Cycle number 8 Byte number 2 Machine codes 8216 zz16 Statement RRF zz Addressing mode Zero page ...

Page 88: ...gain incremented by one and stores the contents of the memory location designated by S in PCL S is again incremented by one and stores the contents of memory location designated by S in PCH Value returns to the original one that was pushed in the stack S S 1 Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 6 Byte number 1 Statement RTI Addressing mode Implied Machine codes 4016 ...

Page 89: ...is instruction increments S by one and stores the contents of the memory location designated by S in PCL S is again incremented by one and the contents of the memory location is stored in PCH PC is incremented by 1 No change Addressing mode Implied Statement RTS Machine codes 6016 Cycle number 6 Byte number 1 ...

Page 90: ...o change No change Z is 1 when the operation result is 0 otherwise Z is 0 C is 1 when the subtracted result is equal to or greater than 0 otherwise C is 0 Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Cycle number 2 3 4 4 5 5 6 6 Byte number 2 2 2 3 3 3 2 2 Machine codes E916 nn16 E516 zz16 F516 zz16 ED16 ll16 hh16 FD16 ll16 hh16 F916 ll16 hh16 E116 zz16 F116 zz16 Statement SBC nn SBC...

Page 91: ...struction sets the designated bit i of A or M No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 5 Byte number 1 2 Machine codes 20i B 16 20i F 16 zz16 Statement SEB i A SEB i zz Addressing mode Accumulator bit Zero page bit ...

Page 92: ... instruction sets C No change No change No change No change No change No change No change 1 Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 1 Machine code 3816 Statement SEC Addressing mode Implied N V T B I D Z C ...

Page 93: ...s instruction set D No change No change No change No change No change 1 No change No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Machine codes F816 Byte number 1 Cycle number 2 Statement SED Addressing mode Implied ...

Page 94: ... No change No change No change 1 No change No change No change SEI SEI SET INTERRUPT DISABLE FLAG Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Cycle number 2 Byte number 1 Machine codes 7816 Statement SEI Addressing mode Implied ...

Page 95: ...s instruction sets T No change No change 1 No change No change No change No change No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Cycle number 2 Byte number 1 Machine codes 3216 Statement SET Addressing mode Implied ...

Page 96: ...n F u n c tio n Sta tu s fla g Cycle number 4 5 5 6 6 7 7 Byte number 2 2 3 3 3 2 2 Statement STA zz STA zz X STA hhll STA hhll X STA hhll Y STA zz X STA zz Y Addressing mode Zero page Zero page X Absolute Absolute X Absolute Y Indirect X Indirect Y Machine codes 8516 zz16 9516 zz16 8D16 ll16 hh16 9D16 ll16 hh16 9916 ll16 hh16 8116 zz16 9116 zz16 ...

Page 97: ...up from this mode No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 1 Machine codes 4216 Statement STP Addressing mode Implied Note If the STP instruction is disabled the cycle number will be 2 same in operation as NOP However disabling this instruction is an optional feature therefore consult the specifications for the particular chip in question ...

Page 98: ...e contents of X in M The contents of X does not change No change Op e ra tio n F u n c tio n Sta tu s fla g Byte number 2 2 3 Cycle number 4 5 5 Machine codes 8616 zz16 9616 zz16 8E16 ll16 hh16 Statement STX zz STX zz Y STX hhll Addressing mode Zero page Zero page Y Absolute ...

Page 99: ...e contents of Y in M The contents of Y does not change No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 4 5 5 Byte number 2 2 3 Machine codes 8416 zz16 9416 zz16 8C16 ll16 hh16 Statement STY zz STY zz X STY hhll Addressing mode Zero page Zero page X Absolute ...

Page 100: ...ot change N is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Cycle number 2 Byte number 1 Machine codes AA16 Statement TAX Addressing mode Implied ...

Page 101: ...t change N is 1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Cycle number 2 Byte number 1 Machine codes A816 Statement TAY Addressing mode Implied N V T B I D Z C Op e ra tio n F u n c tio n Sta tu s fla g ...

Page 102: ...he N and Z N is 1 when bit 7 of M is 1 otherwise N is 0 No change No change No change No change No change Z is 1 when the M content is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C Addressing mode Zero page Statement TST zz Machine codes 6416 zz16 Byte number 2 Cycle number 3 ...

Page 103: ...1 when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Cycle number 2 Byte number 1 Machine codes BA16 Statement TSX Addressing mode Implied Op e ra tio n F u n c tio n Sta tu s fla g N V T B I D Z C ...

Page 104: ...when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 1 Machine codes 8A16 Statement TXA Addressing mode Implied N V T B I D Z C ...

Page 105: ...NDEX REGISTER X TO STACK POINTER S X This instruction stores the contents of X in S No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 1 Machine codes 9A16 Statement TXS Addressing mode Implied ...

Page 106: ... when bit 7 is 1 after the operation otherwise N is 0 No change No change No change No change No change Z is 1 when the operation result is 0 otherwise Z is 0 No change Op e ra tio n F u n c tio n Sta tu s fla g Cycle number 2 Byte number 1 Machine codes 9816 Statement TYA Addressing mode Implied N V T B I D Z C ...

Page 107: ...cillation of the oscillation circuit is not stopped CPU starts its function after the Timer X over flows comes to the terminal count All registers or internal memory contents except Timer X will not change during this mode Of course needs VDD No change Cycle number 2 Byte number 1 Machine codes C216 Addressing mode Implied Statement WIT ...

Page 108: ...d Because an interrupt enable bit is set to 1 interrupts enabled before an interrupt request bit is cleared to 0 4 1 2 Switching of detection edge For the products able to switch the external interrupt detection edge switch it as the following sequence Fig 4 1 1 Switching sequence of detection edge Reason The interrupt circuit recognizes the switching of the detection edge as the change of externa...

Page 109: ...instruction Fig 4 1 2 Distinction sequence of interrupt request bit Data transfer instruction LDM LDA STA STX STY Reason If the BBC or BBS instruction is executed immediately after an interrupt request request distinguish bit of an interrupt request register interrupt request distinguish register is cleared to 0 the value of the interrupt request request distinguish bit before being cleared to 0 i...

Page 110: ...or the I flag which is 1 Fig 4 2 1 Initialization of flags in Processor Status Register 2 How to reference Processor Status Register To reference the contents of the processor status register PS execute the PHP instruction once then read the contents of S 1 If necessary execute the PLP instruction to return the PS to its original status A NOP instruction should be executed after every PLP instruct...

Page 111: ...has set to 1 If the BRK instruction is executed the interrupt disable state is cancelled and it becomes in the interrupt enable state So that the requested interrupts the interrupts that corresponding to their request bits have set to 1 are accepted 4 2 3 Decimal calculations 1 Execution of Decimal calculations The ADC and SBC are the only instructions which will yield proper decimal results in de...

Page 112: ... cleared to 0 if a borrow is generated To determine whether a calculation has generated a carry the C flag must be initialized to 0 before each calculation To check for a borrow the C flag must be initialized to 1 before each calculation Fig 4 2 5 Status flags in decimal mode 4 2 4 JMP instruction When using the JMP instruction in indirect addressing mode do not specify the last address on a page ...

Page 113: ...mings of all address ing modes are described on the following pages In these figures φ SYNC R W RD WR ADDR ADDRL ADDRH and DATA are internal signals of the single chip microcomputer therefore these signals can be investigated only in the microprocessor mode The combination of these signals differs according to the microcomputer s type The following table lists the valid signal for each product Val...

Page 114: ...s Byte length Cycle number Timing CLC CLD CLI CLT CLV DEX DEY INX INY NOP SEC SED SEI SET TAX TAY TSX TXA TXS TYA 1 2 φ PCH PCL 1 Op code PC PC 1 PCH PCL PCL 1 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR Invalid In valid Op code ...

Page 115: ... S 1 00 Note 1 S 2 00 Note 1 FFF4 Note 2 FFF5 Note 2 ADL ADH AA AA PS ADL ADH 01 PCH PCH PCL S PCH S 1 PCL S 2 AA AA PS F4 ADL F5 ADH ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR FF φ Op code Invalid Op code Notes 1 Some products are 01 or content of SPS flag 2 Some products differ the address In valid ...

Page 116: ... Timing 1 PCL PCL 1 PCL 1 PCH PC PC 1 PCH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid In valid Op code Return from standby state is excuted by ex ternal interrupt Return from wait state is excuted by internal or external interrupt ...

Page 117: ...PCH PCH PCL PCL 1 S 00 Note S 1 00 Note S 2 00 Note S 3 00 Note PCL PCH 00 Note S S 1 S 2 PCL S 3 PCH PCL PS PCH PCL Stack PS Stack PCH Stack SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code Note Some products are 01 or content of SPS flag In valid Invalid ...

Page 118: ...1 S S 1 S 2 PCL PCH PCH PCH 00 Note PCH PCH PCL Stack PCH Stack PC PC 1 S 00 Note S 1 00 Note S 2 00 Note PCL PCH PCL 1 PCH PCL 1 PCL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid In valid Op code Invalid Invalid Note Some products are 01 or content of SPS flag ...

Page 119: ...ctions Byte length Cycle number Timing 1 3 PC PC 1 PCH PCH PCL PCL 1 S Aor PS 00 Note A or PS S 00 Note SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid In valid Op code Note Some products are 01 or content of SPS flag ...

Page 120: ...le number Timing PLA PLP 1 4 PCL PCL 1 PCH PCH 00 Note PC PC 1 S 1 00 Note DATA 00 PC 1 L 00 PC 1 L S 1 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA φ Op code Invalid In valid Op code Invalid Note Some products are 01 or content of SPS flag ...

Page 121: ...s Byte length Cycle number Timing ADC nn T 0 AND nn T 0 CMP nn T 0 CPX nn CPY nn EOR nn T 0 LDA nn T 0 LDX nn LDY nn ORA nn T 0 SBC nn T 0 2 2 PCL PCL 1 PCH PCH PC PC 1 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Op code ...

Page 122: ...C UM ULATOR Instructions Byte length Cycle number Timing ASL A DEC A INC A LSR A ROL A ROR A 1 2 PC PC 1 PCH PCH PCL PCL 1 PCL 1 PCH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code In valid ...

Page 123: ...IV E Instructions Byte length 1 With no branch Cycle number Timing BBC i A hhll BBS i A hhll 2 4 PC PC 1 PCH PCH PCL PCL 1 PCL 1 PCL 1 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid In valid Op code In valid In valid ...

Page 124: ...ming 2 6 BBC i A hhll BBS i A hhll PC 2 RR L PC 2 H PC PCH PCH PCL PCL 1 PCL 1 PCL 1 PC 2 H PC 2 H RR 2 2 1 RR PC 1 PC 2 L PC 1 H PC 2 RR PC 2 RR H SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR RR Offset address 1 PC 1 L 2 PC 2 RR L φ Op code Invalid In valid Op code In valid Invalid Invalid ...

Page 125: ...119 AC C UM ULATOR BIT Instructions Byte length Cycle number Timing CLB i A SEB i A 1 2 PC PC 1 PCH PCH PCL PCL 1 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid In valid Op code ...

Page 126: ...ength 1 With no branch Cycle number Timing BBC i zz hhll BBS i zz hhll 3 5 PC PC 1 PCH PCH PCL PCL 1 PCL 2 ADL ADL PCL 2 ADL PCH 00 ADL 00 PC 2 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid In valid Op code In valid DATA DATA ...

Page 127: ... zz hhll 3 7 PC PCH PCH PCL PCL 1 PCL 2 PC 2 H PC 3 H RR 2 2 1 RR PC 1 PC 3 L PC 2 H PC 3 RR L PC 3 H PC 3 RR PC 3 RR H ADL ADL PCL 2 00 PCH ADL 00 PC 2 ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR RR Offset address 1 PC 3 L 2 PC 3 RR L φ Op code Invalid In valid Op code Invalid Invalid DATA DATA ...

Page 128: ... Instructions Byte length Cycle number Timing CLB i zz SEB i zz 2 5 PC PCL PCL 1 PC 1 ADL ADL 00 ADL 00 ADL ADL ADL PCH PCH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA NEW DATA NEW DATA ...

Page 129: ...number Timing ADC zz T 0 AND zz T 0 BIT zz CMP zz T 0 CPX zz CPY zz EOR zz T 0 LDA zz T 0 LDX zz LDY zz ORA zz T 0 SBC zz T 0 TST zz 2 3 PC PC 1 PCH PCH PCL PCL 1 00 ADL ADL 00 ADL ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Op code ...

Page 130: ... length Cycle number Timing 2 5 ASL zz COM zz DEC zz INC zz LSR zz ROL zz ROR zz PC PC 1 PCH PCH PCL PCL 1 00 ADL ADL 00 ADL ADL ADL ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA NEW DATA NEW DATA ...

Page 131: ...nstruction Byte length Cycle number Timing RRF zz 2 8 PC PC 1 PCH PCH PCL PCL 1 00 ADL ADL 00 ADL ADL ADL ADL ADL ADL ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA NEW DATA NEW DATA ...

Page 132: ...RO PAGE Instruction Byte length Cycle number Timing LDM nn zz 3 4 PC PC 1 PCH PCH PCL PCL 1 00 ADL ADL 00 ADL ADL PC 2 PCH PCL 2 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Op code DATA DATA DATA DATA ...

Page 133: ...RO PAGE Instructions Byte length Cycle number Timing 2 4 STA zz STX zz STY zz PC PC 1 PCH PCL PCL 1 00 ADL ADL 00 ADL ADL PCH ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA ...

Page 134: ...th Cycle number Timing 2 15 PC PC 1 ADL ADL X 00 S SPS SYNC R W RD ADDR DATA WR φ Invalid Op code DATA NEW DATA In valid In valid SPS A selected page by stack page selection bit of the CPU mode register Note This instruction cannot be used for any products ...

Page 135: ...ote 2 16 PC PC 1 ADL ADL X 1 00 S SPS ADL X 00 SYNC R W RD ADDR DATA WR SPS A selected page by stack page selection bit of the CPU mode register Note This instruction cannot be used for any products φ Invalid Op code Low order DATA NEW DATA In valid In valid High order DATA ...

Page 136: ...mber Timing ASL zz X DEC zz X INC zz X LSR zz X ROL zz X ROR zz X 2 6 PC PC 1 PCH PCL PCL 1 PCH ADL PC 1 L 00 ADL PC 1 L 00 ADL X ADL X ADL X 00 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA NEW DATA NEW DATA Invalid ADL X ...

Page 137: ...OR zz X T 0 LDA zz X T 0 LDX zz Y LDY zz X ORA zz X T 0 SBC zz X T 0 2 4 Instructions Byte length Cycle number Timing PC PC 1 PCH PCL PCL 1 PCH ADL X orY 00 ADL X or Y ADL PC 1 L 00 ADL PC 1 L 00 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA ...

Page 138: ...s Byte length Cycle number Timing STA zz X STX zz Y STY zz X 2 5 PC PC 1 PCH PCL PCL 1 PCH ADL X or Y 00 ADL X or Y ADL PC 1 L 00 ADL PC 1 L 00 ADL X or Y SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA Invalid ...

Page 139: ...l T 0 AND hhll T 0 BIT hhll CMP hhll T 0 CPX hhll CPY hhll EOR hhll T 0 LDA hhll T 0 LDX hhll LDY hhll ORA hhll T 0 SBC hhll T 0 3 4 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH ADL ADH PCL 2 ADL ADH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code DATA Op code DATA ...

Page 140: ...hll ROL hhll ROR hhll Instructions Byte length Cycle number Timing 3 6 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH ADL ADL PCL 2 ADL ADH ADL ADH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code DATA DATA NEW DATA NEW DATA ...

Page 141: ...135 ABSOLUTE Instruction Byte length Cycle number Timing JMP hhll 3 3 PCH PCL 1 PC PC 1 PCH PCL PC 2 PCH PCL 2 PCL PCL PCH PCH PCH PCL PCL PCH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Op code ...

Page 142: ...hll 3 6 PC PC 1 PCH PCH PCL PCL 1 S 00 Note S 1 00 Note 00 Note S S 1 S PC 2 PCH ADH ADH ADL PCL 2 PC 2 H ADL ADL PC 2 H PC 2 L ADH ADL ADH PC 2 L SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code Note Some products are 01 or content of SPS flag ...

Page 143: ...ions Byte length Cycle number Timing STA hhll STX hhll STY hhll 3 5 PC PC 1 PCH PCH PCL PCL 1 PCH ADH ADH ADL PCL 2 ADL ADL ADL ADH PC 2 ADH ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Invalid Op code ...

Page 144: ...X hhll Y LDY hhll X ORA hhll X or Y T 0 SBC hhll X or Y T 0 Instructions Byte length Cycle number Timing 3 5 PC PC 1 PCH PCL PCL 1 PCH AD L X or Y AD H ADL X or Y ADL ADL PCL 2 ADH ADL X or Y PCH ADH ADH C ADH PC 2 AD L X or Y AD H C C Carry of ADL X or Y SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Invalid Op code ...

Page 145: ...NC hhll X LSR hhll X ROL hhll X ROR hhll X 3 7 PC PC 1 PCH PCH PCL PCL 1 PCH ADH ADH PCL 2 ADL PC 2 ADH C ADL ADH ADL X ADH C ADL X ADH AD L X AD L X AD L X AD L X SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR C Carry of ADL X DATA DATA φ Op code Invalid Op code Invalid NEW DATA NEW DATA ...

Page 146: ...ing 3 6 STA hhll X or Y PC PC 1 PCH PCL PCL 1 PCH AD L X or Y AD H ADL X or Y ADL ADL PCL 2 ADH ADL X or Y PCH ADH ADH C ADH PC 2 AD L X or Y AD H C ADL X or Y SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR C Carry of ADL X or Y DATA DATA φ Op code Invalid Op code Invalid ...

Page 147: ...gth Cycle number Timing 3 5 JMP hhll PC PC 1 PCH PCH PCL PCL 1 PCH BAH ADH PCL 2 BAL PC 2 ADL ADH BAL 1 BAH BAL 1 BAL ADL ADH BAL BAH BAL BAH ADL BAH BAH ADH ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR Op code Op code φ BA Basic address ...

Page 148: ... Instruction Byte length Cycle number Timing 2 4 JMP zz PC PC 1 PCH PCL PCL 1 PCH BAL ADL ADH BAL 00 ADL ADH BAL ADH ADL ADL ADH BAL 1 00 00 BAL 1 BAL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR Op code Op code φ BA Basic address ...

Page 149: ...C 1 PCH PCL PCL 1 BAL ADL ADH BAL 00 ADL ADH BAL ADH ADL ADL ADH BAL 1 00 BAL 1 BAL S S S 1 PC 1 L PCH 00 01 PC 1 H PC 1 L S 00 Note S 1 00 Note PC 1 H SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code Note Some kind types are 01 or content of SPS flag BA Basic address ...

Page 150: ... zz X T 0 CMP zz X T 0 EOR zz X T 0 LDA zz X T 0 ORA zz X T 0 SBC zz X T 0 PC PC 1 PCH PCL PCL 1 BAL ADL BAL X 00 ADH BAL X 1 00 BAL PC 1 L PCH 00 ADH ADL ADH ADL BAL X BAL X 1 PC 1 L 00 ADL ADH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA φ Op code Invalid Op code DATA BA Basic address ...

Page 151: ...mber Timing 2 7 STA zz X PC 1 PCH PCL PCL 1 BAL ADL ADL ADH ADH ADL ADL ADH BAL X 1 00 BAL BAL X 1 PC 1 L PCH 00 PC BAL X 00 PC 1 L 00 ADH ADL BAL X SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA φ Op code Invalid Op code DATA BA Basic address Invalid ...

Page 152: ... T 0 SBC zz Y T 0 Instructions Byte length Cycle number Timing 2 6 PC PC 1 PCH PCL PCL 1 PCH ADH ADH ADL ADH C ADL ADH ADL Y ADH C ADL Y ADH BAL 1 ADL Y BAL BAL 00 BAL BAL 00 BAL 1 00 ADL Y SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR C Carry of ADL Y DATA DATA φ Op code Invalid Op code BA Basic address ...

Page 153: ...2 7 STA zz Y PC PC 1 PCH PCL PCL 1 PCH ADH ADH ADL ADH C ADL ADH ADL Y ADH C ADL Y ADH BAL 1 AD L Y BAL BAL 00 BAL BAL 00 BAL 1 00 AD L Y AD L Y SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR C Carry of ADL Y DATA DATA φ Op code Invalid Op code BA Basic address Invalid ...

Page 154: ... hhll BEQ hhll BMI hhll BNE hhll BPL hhll BVC hhll BVS hhll Instructions Byte length 1 With no branch Cycle number Timing 2 2 PC PC 1 PCH PCH PCL PCL 1 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid In valid Op code ...

Page 155: ... hhll Instructions Byte length 2 With branch Cycle number Timing 2 4 PC PCH PCH PCL 1 PC 1 H PC 2 H RR RR PC 1 PC 2 L PC 1 H PC 2 RR L PC 2 H PC 2 RR PCH PC 2 L PC 2 RR H RR Offset value PC 2 RR L PC 2 RR L SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code Invalid ...

Page 156: ...le number Timing 2 4 BRA hhll φ PC PCL PCH PCL 1 PC 1 H PC 2 H RR RR PC 1 PC 2 L PC 1 H PC 2 RR L PC 2 H PC 2 RR PC 2 RR H PCH PC 2 L PC 2 RR L PC 2 RR L SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR RR Offset value Op code Invalid Op code Invalid ...

Page 157: ...g JSR hhll 2 5 PC PC 1 PCH PCL PCL 1 S 00 Note S 1 00 Note 00 Note S S 1 S PCH PC 1 L PC 1 H BAL BAL FF PC 1 H PC 1 L BAL BAL FF SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code Note Some products are 01 or content of SPS flag BA Basic address ...

Page 158: ...te length Cycle number Timing 2 5 ADC nn T 1 AND nn T 1 EOR nn T 1 ORA nn T 1 SBC nn T 1 PCL PCL 1 PCH PCH PC PC 1 DATA 2 00 DATA 1 X X X X 00 DATA 1 DATA 2 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR φ Op code Invalid Op code NEW DATA NEW DATA ...

Page 159: ... IM M ED IATE T 1 T 1 CMP nn T 1 Instruction Byte length Cycle number Timing 2 3 PC PC 1 PCH PCH PCL PCL 1 X 00 00 X SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 DATA 2 φ Op code Op code ...

Page 160: ...IM M ED IATE T 1 T 1 Instruction Byte length Cycle number Timing LDA nn T 1 2 4 PC PC 1 PCH PCH PCL PCL 1 00 X X X 00 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Op code Invalid DATA DATA ...

Page 161: ...ycle number Timing 2 6 ADC zz T 1 AND zz T 1 EOR zz T 1 ORA zz T 1 SBC zz T 1 PC PC 1 PCH PCH PCL PCL 1 X 00 00 X X X ADL ADL ADL 00 ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Invalid Op code NEW DATA NEW DATA DATA 2 ...

Page 162: ...T 1 ZERO PAGE T 1 T 1 Instruction Byte length Cycle number Timing 2 4 PC PC 1 PCH PCH PCL PCL 1 X 00 00 X ADL ADL ADL 00 ADL SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Op code DATA 2 ...

Page 163: ...E T 1 T 1 Instruction Byte length Cycle number Timing 2 5 LDA zz T 1 PC PC 1 PCH PCH PCL PCL 1 X 00 00 X ADL ADL ADL 00 ADL X SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Invalid Op code DATA DATA ...

Page 164: ...ADC zz X T 1 AND zz X T 1 EOR zz X T 1 ORA zz X T 1 SBC zz X T 1 2 7 PC PC 1 PCH PCH PCL PCL 1 X 00 00 X ADL ADL X ADL X 00 ADL X X PC 1 L 00 PC 1 L SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Invalid Op code NEW DATA NEW DATA DATA 2 Invalid ...

Page 165: ...ruction Byte length Cycle number Timing CMP zz X T 1 2 5 PC 1 PCH PCH PCL PCL 1 X 00 00 X ADL AD L X ADL X 00 ADL PC 1 L 00 PC 1 L PC SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Invalid Op code DATA 2 ...

Page 166: ... T 1 T 1 Instruction Byte length Cycle number Timing 2 6 PC 1 PCH PCH PCL PCL 1 X 00 00 X ADL ADL X ADL X 00 ADL PC 1 L 00 PC 1 L PC X SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Invalid Op code Invalid DATA DATA ...

Page 167: ...DC hhll T 1 AND hhll T 1 EOR hhll T 1 ORA hhll T 1 SBC hhll T 1 3 7 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH ADL PCL 2 ADL ADH X X X ADH X 00 00 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Op code NEW DATA NEW DATA DATA 2 Invalid ...

Page 168: ...ruction Byte length Cycle number Timing CMP hhll T 1 3 5 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH ADL PCL 2 ADL ADH X ADH X 00 00 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Op code DATA 2 ...

Page 169: ...uction Byte length Cycle number Timing LDA hhll T 1 3 6 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH ADL PCL 2 ADL ADH X ADH X 00 00 X SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Invalid Op code DATA DATA ...

Page 170: ...1 Instructions Byte length Cycle number Timing 3 8 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH PCL 2 X ADH X 00 00 X ADH C X AD L X or Y AD H ADL X or Y ADL X or Y AD L X or Y AD H C SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Op code NEW DATA NEW DATA DATA 2 Invalid Invalid C Carry of ADL X or Y ...

Page 171: ...ing CMP hhll X or Y T 1 3 6 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH PCL 2 X ADH X 00 00 ADH C ADL X or Y ADH ADL X or Y ADL X or Y ADL X or Y ADH C SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 φ Op code Op code DATA 2 Invalid C Carry of ADL X or Y ...

Page 172: ...ing LDA hhll X or Y T 1 3 7 PCH PCL 1 PC PC 1 ADL PCH PCL ADL PC 2 ADH PCH ADH PCL 2 X ADH X 00 00 ADH C ADL X or Y ADH ADL X orY ADL X or Y ADH C X ADL X orY SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA φ Op code Op code Invalid C Carry of ADL X or Y Invalid DATA DATA ...

Page 173: ... ORA zz X T 1 SBC zz X T 1 2 9 PCH PCL 1 PC PC 1 BAL PCH PCL AD L ADH ADH X ADL X 00 00 BAL X 00 PC 1 L AD H AD L X X BAL BAL X 1 PC 1 L 00 BAL X 00 BAL X 1 00 ADL ADH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 1 φ Op code Op code DATA 1 BA Basic address Invalid DATA 2 Invalid NEW DATA DATA 2 NEW DATA ...

Page 174: ...ing 2 7 CMP zz X T 1 PCH PCL 1 PC PC 1 BAL PCH PCL ADH ADH X ADL X 00 00 BAL X 00 PC 1 L BAL PC 1 L 00 BAL X 00 BAL X 1 ADL ADH ADL ADH ADL BAL X 1 00 SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 1 φ Op code Op code DATA 1 BA Basic address Invalid DATA 2 DATA 2 ...

Page 175: ... number Timing 2 8 PCH PCL 1 PC PC 1 BAL PCH PCL AD L ADH ADH X ADL X 00 00 BAL X 00 PC 1 L AD H AD L X BAL BAL X 1 PC 1 L 00 BAL X 00 BAL X 1 00 ADL ADH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA φ Op code Op code DATA BA Basic address Invalid DATA Invalid DATA ...

Page 176: ... T 1 SBC zz Y T 1 2 9 PCH PCL 1 PC PC 1 BAL PCH PCL AD L ADH ADH C X ADL 00 00 AD H X BAL ADL Y ADH C BAL BA L 1 AD L Y AD L Y X ADH BAL 00 BAL 1 00 X 00 ADL Y ADH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 DATA 2 φ Op code Invalid Op code NEW DATA NEW DATA Invalid C Carry of ADL Y BA Basic address ...

Page 177: ... Y T 1 2 7 PCH PCL 1 PC PC 1 BAL PCH PCL AD L ADH ADH C ADL 00 00 AD H X BAL ADL Y ADH C BAL BAL 1 AD L Y AD L Y ADH BAL 00 BAL 1 00 X 00 ADL Y ADH SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA 2 DATA 1 DATA 1 DATA 2 φ Op code Invalid Op code C Carry of ADL Y BA Basic address ...

Page 178: ...iming 2 8 PCH PCL 1 PC PC 1 BAL PCH PCL AD L ADH ADH C ADL 00 00 AD H X BAL ADL Y ADH C BAL BA L 1 AD L Y AD L Y ADH BAL 00 BAL 1 00 X 00 ADL Y ADH X SYNC R W RD ADDR DATA ADDRH ADDRL DATA WR DATA DATA DATA φ Op code Invalid Op code C Carry of ADL Y BA Basic address DATA Invalid ...

Page 179: ...A zz LDA zz X LDA hhII LDA hhII X LDA hhII Y LDA zz X LDA zz Y LDX nn LDX zz LDX zz Y LDX hhII LDX hhII Y LDY nn LDY zz LDY zz X LDY hhII LDY hhII X LDM nn zz STA zz STA zz X STA hhII STA hhII X STA hhII Y STA zz X STA zz Y STX zz STX zz Y STX hhII STY zz STY zz X STY hhII TAX TXA TAY TYA TSX TXS PHA PHP PLA PLP Parameter CYCLE NUMBER Load Store Transfer Data Transfe r Classification FUNCTION SYMB...

Page 180: ... 1 B2 B3 1 1 1 0 1 1 0 1 B2 B3 1 1 1 1 1 0 0 1 B2 B3 1 1 1 0 0 0 0 1 B2 1 1 1 1 0 0 0 1 B2 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 0 B2 1 1 1 1 0 1 1 0 B2 1 1 1 0 1 1 1 0 B2 B3 1 1 1 1 1 1 1 0 B2 B3 Classification SYMBOL FUNCTION A A nn C A A M C where M zz A A M C where M zz X A A M C where M hhII A A M C where M hhII X A A M C where M hhII Y A A M C where M zz X 1 zz X A A M C where M zz 1 zz Y A A nn C A...

Page 181: ... A M where M zz X 1 zz X A A M where M zz 1 zz Y _ _ _ _ _ M M where M zz A M where M zz A M where M hhII M 0 where M zz A nn A M where M zz A M where M zz X A M where M hhII A M where M hhII X A M where M hhII Y A M where M zz X 1 zz X A M where M zz 1 zz Y X nn X M where M zz X M where M hhII Y nn Y M where M zz Y M where M hhII FUNCTION 0 0 1 0 1 0 0 1 B2 0 0 1 0 0 1 0 1 B2 0 0 1 1 0 1 0 1 B2 0...

Page 182: ...0 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 B2 0 1 1 1 0 1 1 0 B2 0 1 1 0 1 1 1 0 B2 B3 0 1 1 1 1 1 1 0 B2 B3 0 0 1 0 1 0 1 0 0 0 1 0 0 1 1 0 B2 0 0 1 1 0 1 1 0 B2 0 0 1 0 1 1 1 0 B2 B3 0 0 1 1 1 1 1 0 B2 B3 0 0 0 0 0 ASL A ASL zz ASL zz X ASL hhII ASL hhII X LSR A LSR zz LSR zz X LSR hhII LSR hhII X ROL A ROL zz ROL zz X ROL hhII ROL hhII X ROR A ROR zz ROR zz X ROR hhII ROR hhII X RRF zz CLB i A CLB i z...

Page 183: ...hII BBS i A hhII BBS i zz hhII BCC hhII BCS hhII BNE hhII BEQ hhII BPL hhII BMI hhII BVC hhII BVS hhII RTI RTS BRK NOP WIT STP Previous status in stack 1 1 PC PC 2 Rel PC hhII PCL hhII PCH hhII 1 PCL zz PCH zz 1 M S PCH S S 1 M S PCL S S 1 and PC hhII M S PCH S S 1 M S PCL S S 1 PCL zz and PCH zz 1 M S PCH S S 1 M S PCL S S 1 PCL II and PCH FF When Ai 0 PC PC 2 Rel Where i 0 7 When Ai 1 PC PC 2 Wh...

Page 184: ...s 0 255 Zero page address 0 255 Date at 0 255 Data at 0 7 Data at 0 7 Second byte of instruction Third byte of instruction Relative address Break address Direction of data transfer Contents of register of memory Add Subtract Multiplication Division Logical OR Logical AND Logical Exclusive OR Negative Stable flag after execution Variable flag after execution Notes 1 Listed function is when T 0 When...

Page 185: ...X TSX DEX NOP 1011 B SEB 0 A CLB 0 A SEB 1 A CLB 1 A SEB 2 A CLB 2 A SEB 3 A CLB 3 A SEB 4 A CLB 4 A SEB 5 A CLB 5 A SEB 6 A CLB 6 A SEB 7 A CLB 7 A 1101 D ORA ABS ORA ABS X AND ABS AND ABS X EOR ABS EOR ABS X ADC ABS ADC ABS X STA ABS STA ABS X LDA ABS LDA ABS X CMP ABS CMP ABS X SBC ABS SBC ABS X 3 byte instruction 2 byte instruction 1 byte instruction Note Some products unuse these instructions...

Page 186: ...180 MEMORANDUM 740 Family Iist of Instruction Codes ...

Page 187: ...by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1997 MITSUBISHI ELECTRIC CORPORATION ...

Page 188: ... HEAD OFFICE MITSUBISHI DENKI BLDG MARUNOUCHI TOKYO 100 TELEX J24532 CABLE MELCO TOKYO Software Manual 740 Family 1997 MITSUBISHI ELECTRIC CORPORATION New publication effective Sep 1997 Specifications subject to change without notice ...

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