31
AD C
AD C
AD
D WITH
C
ARRY
When (T) = 0, (A)
←
(A) + (M) + (C)
(T) = 1, (M(X))
←
(M(X)) + (M) + (C)
When T = 0, this instruction adds the contents M, C, and A;
and stores the results in A and C.
When T = 1, this instruction adds the contents of M(X), M and
C; and stores the results in M(X) and C. When T=1, the
contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory where is indicated by
X.
N is 1 when bit 7 is 1 after the operation; otherwise it is
0.
V is 1 when the operation result e127 or –128;
otherwise it is 0.
No change
No change
No change
No change
Z is 1 when the operation result is 0; otherwise it is 0.
C is 1 when the result of a binary addition exceeds 255 or
when the result of a decimal addition exceeds 99;
otherwise it is 0.
Op e r a t io n :
F u n c t io n :
St a t u s fla g :
N :
V :
T :
B :
I :
D :
Z :
C :
Byte number
2
2
2
3
3
3
2
2
Statement
∆
ADC
∆
#$nn
∆
ADC
∆
$zz
∆
ADC
∆
$zz,X
∆
ADC
∆
$hhll
∆
ADC
∆
$hhll,X
∆
ADC
∆
$hhll,Y
∆
ADC
∆
($zz,X)
∆
ADC
∆
($zz),Y
Machine codes
69
16
, nn
16
65
16
, zz
16
75
16
, zz
16
6D
16
, ll
16
, hh
16
7D
16
, ll
16
, hh
16
79
16
, ll
16
, hh
16
61
16
, zz
16
71
16
, zz
16
Cycle number
2
3
4
4
5
5
6
6
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Notes 1: When T=1, add 3 to the cycle number.
2: When ADC instruction is executed in the decimal operation mode (D
= 1), decision of C is delayed. Accordingly, do not execute the
instruction which operates C such as SEC, CLC, etc.
