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MELSEC-Q
6 COMMUNICATION TIME
6. COMMUNICATION TIME
6.1 Bus Cycle Time
(1) Bus cycle time when there is one master station
An explanation of the bus cycle time when there is one master station is given in
the following diagram. The following diagram (Fig. 6.1) shows an example for
when there are 3 slave stations.
Time
Buffer memory
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Internal buffer
Slave1
Slave2
Slave3
Treq(1)
Tres(1)
Treq(2)
Tres(2)
Treq(3)
Tres(3)
Max Tsdr(1)
Max Tsdr(2)
Max Tsdr(3)
Lr
Pt(1)
Pt(2)
Pt(3)
Tsdi(M)
Tsdi(M)
Tsdi(M)
MSI(Min Slave Interval)
Bc
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Fig. 6.1 The bus cycle time when there is one master station
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