miniDSP Ltd, Hong Kong /
/ Features and specifications subject to change without prior notice
18
4
I/O
I
NTERFACES
Interfacing to the miniSHARC is accomplished through I2s, also known as Inter IC Sound, an electrical serial bus
used to interface digital audio devices at the chip and circuit board level. The miniSHARC circuit board provides
audio input and output via I2S pins on the J2 30-pin header. An SPDIF interface is also provided on J2.
While miniDSP provides a number of prebuilt I2S interfaces (described in Section 3), system integrators and
advanced DIY enthusiasts may wish to implement their own input-output using the I2S interfaces.
4.1
I2S
OVERVIEW
An I2S interface consists of up to three clocks, and a data line for each pair of channels.
There are three types of clock:
MCLK
The master clock that the miniSHARC uses internally. This clock is always provided as an output
by the miniSHARC, and connected circuitry can choose whether or not to use it.
LRCLK
The frame synchronization clock, also known as the word clock. This clock is equal to the
sampling frequency (Fs) of the audio signal.
BCLK
The bit clock (also known as shift clock or system clock). This is always equal to 64 x Fs.
Table 4 summarizes the relation between the clocks for the 48 and 96 kHz plugins.
Table 4. I2S clock ratios
Plugin sample rate (LRCLK) Master clock (MCLK) Bit clock (BCLK) MCLK/LRCLK BCLK/LRCLK
48 kHz
24.576 MHz
3.072 MHz
512
64
96 kHz
24.576 MHz
6.144 MHz
256
64
The timing of data lines is determined by the bit clock and the word clock, as illustrated in the following diagram:
The miniSHARC board has four input I2S data lines and four I2S output data lines. Note, however, that the input
data lines for channels 5 though 8 are not accessible in the current firmware and plugins. The I2S data line for
channels 3 and 4 is used by the SPDIF input, and is accessible by the miniSHARC 4x8 plugins (both 48 kHz and 96
kHz versions).
