Microsemi DS3106DK, Manual

Page: 9 / 32

_________________________________________________________________________________________ DS3106DK
9
Table 4-1. Mapping Between Input Clock Software Fields and DS3106 Register Fields
SOFTWARE FIELD DS3106 REGISTER FIELDS
Input Clock Status LEDs 3 and 4
ISR2 register
LED red when ACT = 1, LOCK = 0
LED green when ACT = 0, LOCK = 0
LED magenta when LOCK = 1
FREQ 3 and 4 ICR3 and ICR4:FREQ[3:0]
LK MODE 3 and 4 ICR3 and ICR4:LOCK8K, and DIVN
SEL REF PTAB1:SELREF
FREQ (ppm) FREQ1, FREQ2, and FREQ3 registers concatenated
PHASE (deg) PHASE1 and PHASE2 register concatenated
LEAKY BUCKET SETTINGS LBxU, LBxL, BLxS, LBxD (x = 1 to 4)
DIVN DIVN1, DIVN2
8K Polarity TEST1:8KPOL
Freq Range Enable MCR1:FREN
4.3 T0 DPLL
The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE text box. The STATE and
SRFAIL buttons represent latched status bits in the device. When the button is red, the corresponding latched
status bit has been set in the DS3106. Pressing the button clears the latched status bit and changes the color of
the button back to green. The
STATE button indicates that the state of the T0 DPLL has changed since the last
time the button was pressed. SRFAIL indicates that the selected reference has failed since the last time the button
was pressed. The state of the T0 DPLL can be forced using the combo box to the left of the STATE text box.
The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3106 T0 DPLL). The
acquisition and locked bandwidths are set by the ABW and LBW fields, respectively, and the damping factor is set
by the DAMP field. The acquisition bandwidth is only used if AUTOBW is checked. If the frequency of the T0
DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of
the main window), the SOFTLIM LED turns red.
When the Freerun Holdover box is checked, the T0 DPLL will holdover at 0ppm with respect to the REFCLK
oscillator rather than at the long-term frequency average of the last valid input clock. When the Freerun Holdover
box is not checked, holdover type can be set to instant or averaged. The PALARM status LED and the phase
detector 2 ( PD2 ) fields are advanced topics. See Table 4-2 and the DS3106 data sheet for more details.
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3106 Register Fields
SOFTWARE FIELD DS3106 REGISTER FIELDS
STATE combo box MCR1:T0STATE
STATE status box OPSTATE:T0STATE
FREQ Fixed by T0 DPLL architecture
ABW T0ABW
LBW T0LBW
DAMP T0CR2:DAMP
STATE latched status button MSR2:STATE
SRFAIL MSR2:SRFAIL
PALARM TEST1:PALARM
SOFTLIM OPSTATE:T0SOFT
AUTOBW MCR9:AUTOBW
LIMINT MCR9:LIMINT
Freerun Holdover MCR3:FRUNHO
Holdover Type HOCR3:AVG
HO Ready VALSR2:HORDY
PD2 Enable T0CR3:PD2EN
PD2G T0CR3:PD2G
PD2G8K T0CR2:PD2G8K