_________________________________________________________________________________________ DS3106DK
10
4.4
T0 APLL and T0 APLL2
The
Input Freq
field configures the frequency of the T0 APLL DFS (refer to the DS3106 data sheet for details). The
APLL output frequency is always four times the input frequency. When the
Input Freq
field is changed, the
Output
Freq
field changes to match, and all the T0 options in the OC3 and OC6 output clock combo boxes also change to
frequencies derived from the new T0 APLL frequency. These changes match what happens in the DS3106.
In normal operation the T0 APLL2 has a fixed output frequency of 312.5MHz (twice the standard XGMII clock rate).
The rate is displayed in the
T0 APLL2
Output Freq
text box.
Whenever the T0 APLL DFS or the T0 APLL2 DFS are configured for programmable DFS operation (see Section
), their respective
Input Freq
and
Output Freq
fields specify their frequencies with a “P” prefix to indicate that
programmable DFS mode is enabled.
Table 4-3. Mapping Between T0 APLL Software Fields and DS3106 Register Fields
SOFTWARE FIELD
DS3106 REGISTER FIELDS
Input Freq
T0CR1:T0FREQ
Output Freq
Derived by software from Input Freq
4.5
T4 APLL
The
Input Freq
field in the
T4 APLL
box configures the frequency of the T4 APLL DFS (refer to the DS3106 data
sheet for details). The APLL output frequency is always four times the input frequency. When the
Input Freq
field
is changed, the
Output Freq
field changes to match, and all the T4 options in the OC3 and OC6 output clock
combo boxes also change to frequencies derived from the new T4 APLL frequency. These changes match what
happens in the DS3106.
Whenever the T4 APLL DFS is configured for programmable DFS operation (see Section
), the
Input Freq
and
Output Freq
fields specify their frequencies with a “P” prefix to indicate that programmable DFS mode is enabled
for the T4 APLL DFS.
Table 4-4. Mapping Between T4 APLL Software Fields and DS3106 Register Fields
SOFTWARE FIELD
DS3106 REGISTER FIELDS
Input Freq
T0CR1:T0FT4
Output Freq
Derived by software from Input Freq
4.6
Output Clocks
The fields in the
OUTPUT CLOCKS
box configure the DS3106’s output clocks. The
DIG1
and
DIG2
fields
configure the Digital1 and Digital2 frequency options for OC3 and OC6 (refer to the DS3106 data sheet for details).
The
OC3
and
OC6
fields specify the output frequencies for outputs OC3 and OC6. Note that when the T0 APLL
setting is changed, the frequencies of all the T0 options in the
OC3
and
OC6
fields automatically change to
frequencies derived from the new T0 APLL frequency. Similarly, when the T4 APLL setting is changed, the
frequencies of all the T4 options in the
OC3
and
OC6
fields automatically change to frequencies derived from the
new T4 APLL frequency. These changes match what happens in the DS3106.
Whenever the T0 APLL DFS, T4 APLL DFS, or T0 APLL2 DFS are configured for programmable DFS operation
(see Section
), the T0, T4, and T02 options, respectively, in the
OC3
and
OC6
fields change to frequencies
derived from the programmable DFS settings. These options all have a “P” prefix, for example, “PT0” or “PT4” to
indicate that they are controlled by the programmable DFS mode. Similarly, whenever the DIG1 DFS or the DIG2
