Microsemi DS3106DK Manual Download | Manualshive

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01

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021907

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RELEASE

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REVIEW

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030907

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ADDED

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REVISION

HISTORY

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051707

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GENERAL

CLEANUP,

RELEASE

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DATASHEET,

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ON

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OSC,

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DESIGN

REVIEW

B0

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052907

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BELOW

SONSDH

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DS3104DK01B0

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Summary of Contents for DS3106DK

Page 1: ... SMB Connectors and Termination Ease Connectivity Careful Layout for Analog Signal Paths On Board Stratum 3 Oscillator with Footprints for Stratum 3E and Stratum 4 Oscillators On Board Microcontroller and Included Software Provide Point and Click Access to the DS3106 Register Set LEDs for Interrupt Power Supplies and Lock Status Banana Jack VDD and GND Connectors Support Use of Lab Power Supplies ...

Page 2: ...D LINE OPTIONS 7 4 OVERVIEW OF THE SOFTWARE INTERFACE 8 4 1 GLOBAL CONFIGURATION 8 4 2 INPUT CLOCK MONITOR DIVIDER AND SELECTOR 8 4 3 T0 DPLL 9 4 4 T0 APLL AND T0 APLL2 10 4 5 T4 APLL 10 4 6 OUTPUT CLOCKS 10 4 7 DPLL FREQUENCY LIMITS PHASE DETECTORS DPLL LOCK CRITERIA 11 4 8 REFCLK CALIBRATION 11 4 9 PROGRAMMABLE DFS 12 4 10 I O PINS 14 4 11 REGISTER VIEW WINDOW 15 4 12 CONFIGURATION SCRIPTS AND L...

Page 3: ...and DS3106 Register Fields 9 Table 4 2 Mapping Between T0 DPLL Software Fields and DS3106 Register Fields 9 Table 4 4 Mapping Between T0 APLL Software Fields and DS3106 Register Fields 10 Table 4 5 Mapping Between T4 APLL Software Fields and DS3106 Register Fields 10 Table 4 6 Mapping Between Output Clock Software Fields and DS3106 Register Fields 11 Table 4 7 Mapping Between DPLL Software Fields ...

Page 4: ...nexpensive XOs to higher performance TCXOs The top edge contains from left to right power supply connectors DC DC converters and power indicator LEDs reset pushbutton serial connector and USB connector An on board DS87C520 microcontroller is located near the USB connector The bottom edge of the board is occupied by a JTAG connector and LED indicators The DS3106DK has the same PCB design as demo ki...

Page 5: ...6DK Jumpers JMP62 and JMP63 select the computer interface to be USB or RS232 Jumper JMP5 upper left selects whether the board should be powered from the USB connector or from the power supply jacks J3 or J13 J19 LEDs DS1 DS4 upper left indicate the labeled power supply is operational LED DS16 upper right indicates the microprocessor is operational LEDs DS5 DS6 and DS10 lower middle indicate the st...

Page 6: ...modem cable Null modem cables prevent proper operation 4 Attach the appropriate AC power supply prongs to the included international power supply 5 Plug the power supply into an AC power outlet and connect the DC output of the supply to connector J3 upper left corner in Figure 1 1 At this point the power indicator LEDs DS1 DS4 should be lit Microcontroller status LED DS16 to the right of the USB c...

Page 7: ...d the hardware the ID field in the upper left corner should indicate 3106 rev x where x 0 for a revision A1 device and x 1 for a revision A2 device The demo kit software always starts in demo mode with the DEMO MODE checkbox in the upper left corner checked to allow a user to look at the software without having the DK hardware connected to the PC To connect the software with the demo kit hardware ...

Page 8: ...s associated with input clocks IC3 and IC4 Just to the right of the input clock numbers 3 and 4 are software LEDs that indicate the state of each input as reported by its input monitor These LEDs are red in the absence of any other condition When a clock of the correct frequency is applied to an input the associated LED turns green when activity is detected If an input is disqualified by one of th...

Page 9: ...be forced using the combo box to the left of the STATE text box The frequency of the T0 DPLL is displayed in the FREQ field fixed at 77 76MHz for the DS3106 T0 DPLL The acquisition and locked bandwidths are set by the ABW and LBW fields respectively and the damping factor is set by the DAMP field The acquisition bandwidth is only used if AUTOBW is checked If the frequency of the T0 DPLL s selected...

Page 10: ...put clock combo boxes also change to frequencies derived from the new T4 APLL frequency These changes match what happens in the DS3106 Whenever the T4 APLL DFS is configured for programmable DFS operation see Section 4 9 the Input Freq and Output Freq fields specify their frequencies with a P prefix to indicate that programmable DFS mode is enabled for the T4 APLL DFS Table 4 4 Mapping Between T4 ...

Page 11: ...urns red but the selected reference is not disqualified If the FLLOL frequency limit loss of lock box is checked in the DPLL LOCK CRITERIA box when the selected reference exceeds the hard limit the DPLL will lose lock transition to LOL state The remaining fields are advanced topics See Table 4 6 and the DS3106 data sheet for more details Table 4 6 Mapping Between DPLL Software Fields and DS3106 Re...

Page 12: ...f the software Frequencies of 77 76MHz or above must be synthesized using an APLL DFS and its associated APLL and are typically brought out on differential output clock pin s If a group of custom clock rates that are related to one another by factors of 1 2 4 6 8 10 12 16 20 48 or 64 are needed often the highest frequency clock can be produced through one of the APLL DFS blocks and then various lo...

Page 13: ..._________________________________________________________________________________________DS3106DK 13 Figure 4 2 Software Programmable DFS Window ...

Page 14: ...DS3106 data sheet for details Figure 4 3 Software I O Pins Window Table 4 8 Mapping Between I O Pins Software Fields and DS3106 Register Fields SOFTWARE FIELD DS3106 REGISTER FIELDS GPIO1 to GPIO4 Config GPCR GPIOxD and GPIOxO GPIO1 to GPIO4 Status GPSR GPIOx INTREQ Mode INTCR LOS GPO INTREQ Polarity INTCR POL INTREQ Open Drain Enable INTCR OD LOCK Pin Enable MCR1 LOCKPIN LOS Pin Enable MCR10 SRFP...

Page 15: ... the bottom of the window Due to the limited speed of the serial port the demo kit software does not continually poll every register and does not make real time updates to the data displayed on the Register View screen Registers can be manually read as described below The Register View window supports the following actions Read a register Select the register in the register map Read a register fie...

Page 16: ...the DK software fields press the Log File button and use File Save As in Notepad to save a copy of the entire log file to a different file name A partial configuration file only affects a subset of the DS3106 device settings To make a partial configuration script press the Log File button to view the log file press Ctrl End to jump to the end of the file and add to the end of the file a carriage r...

Page 17: ... 50V GEN PURPOSE SILICON GEN 1N4001 D2 D7 2 SCHOTTKY DIODE 1 AMP 40 VOLT IRF 10BQ040 DS1 DS4 DS6 5 SMD green LEDs PAN LN1351C DS5 DS10 2 SMD red LEDs PAN LN1251C DS16 1 SMD green LED PAN LN1351C J1 J6 J7 J22 J27 J40 J41 7 CONNECTOR SMB 50 OHM VERTICAL 5PIN AMP 413990 1 J3 1 CONN 2 1MM 5 5MM PWRJACK RT ANGLE PCB closed frame high current 24VDC 5A CUI INC PJ 002AH J13 1 SOCKET BANANA PLUG HORIZONTAL...

Page 18: ...TUFF NA NA U1 U2 U5 U13 U14 U23 U24 U28 8 L_TINYLOGIC HIGH SPEED 2 INPUT OR GATE 5 PIN SOT23 FAI NC7SZ32M5 U3 1 IC LINE CARD TIMING 40 C to 85 C 64 PIN QFP DAL DS3106 U4 U6 2 LINEAR REGULATOR 3 3V 16 PIN TSSOP EP MAX MAX1793EUE 33 U7 U25 2 L_TINYLOGIC HIGH SPEED 2 INPUT XOR GATE 5 PIN SOT23 FAI NC7SZ86M5 U8 1 LINEAR REGULATOR 1 8V 16 PIN TSSOP EP MAX MAX1793EUE 18 U26 1 IC LINEAR REGULATOR 1 5W 2 ...

Page 19: ... Y3 1 OSCILLATOR CRYSTAL CLOCK XO 1613 3 3V CMOS LOW JITTER 12 8MHz 4 PIN SMD DO NOT POPULATE SAR S1613A 12 8000 Y4 1 OSCILLATOR CRYSTAL CLOCK XO 1633 3 3V CMOS LOW JITTER 12 8MHz 4 PIN SMD DO NOT POPULATE SAR S1633A 12 8000 Y7 1 XTAL LOW PROFILE 11 0592MHz PLE LP49 33 11 0592M 6 Appendix 2 Schematics The schematics are featured in the following pages 7 Document Revision History REVISION DATE DESC...

Page 20: ...TREQ SRFAIL IC6POS IC6NEG IC4 SONSDH TEST SONSDH MFSYNC OC7NEG NA NA NA LOCK DNP DNP 10K CPOL CPHA OC5POS SYNC3 SYNC2 IC9 IC3 IC1NEG WDT 0 0 FSYNC OC7POS SCLK SDI VPLL1 1UF 1UF 1UF VPLL3 VPLL2 LOCK SRCSW OC6NEG OC5 1UF IC5POS IC2NEG IC2POS OC6POS VPLL4 CPHA SDO 330 NA NA INTREQ JTRST IC1POS DUT18 10K JTCLK TEST SRCSW CS 0 0 330 OC5B OC5NEG IC5NEG SYNC1 330 CPOL JTMS PAGE DATE TITLE ENGINEER A A B ...

Page 21: ... OC2B OC3B SDI SYNC1 IC6NEG IC6POS IC5NEG IC5POS IC4 IC3 INTREQ TEST SONSDH SYNC2 PORNOT I26 PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 DS3105_U2 QFP JTRST TEST RST SYNC1 SYNC2 GPIO4 SONSDH IC9 IC6NEG SDI SDO VDD2 VDD4 VDDIO1 IC5NEG O3F1 SRFAIL VDDIO2 VDDIO3 VDDIO4 SRCSW VSS6 VSS7 OC3 FSYNC IC6POS IC5POS IC4 REFCLK VSS1 CPHA CS SCLK MFSYNC O6F1 GPIO2 O6F2 GPIO3 O3F2 L...

Page 22: ... C19 2 1 C11 2 4 16 3 12 13 5 14 1 11 15 U29 1 J14 2 1 R16 2 1 R18 4 1 3 2 Y2 2 1 C2 2 1 R28 1 J12 1 J11 1 J10 2 1 R32 1 J9 2 1 R31 1 J8 2 1 R30 1 J7 2 1 R29 1 J6 VCC SYNC2 100K VCC VCC VCC VCC 51 1 51 1 51 1 REFCLK NA 1UF NA 12 8MHZ DNP DNP OSC33 12 8MHZ_3 3V 12 8MHZ_3 3V 12 8MHZ_3 3V_XO 1UF DNP 12 8MHZ_3 3V_XO REFCLK DNP OSC33 DNP 1UF OSC33 33 2 100UF DNP IC3 51 1 51 1 IC4 IC8 10K 51 1 IC9 SYNC3...

Page 23: ...P12 1 TP11 2 1 R24 2 1 R23 1 TP10 2 1 R22 1 TP9 2 1 R21 2 1 JMP8 2 1 JMP7 1 TP56 1 TP55 1 TP54 1 TP53 1 J37 1 TP52 1 TP51 1 J36 2 1 R68 2 1 R67 2 1 JMP37 2 1 JMP36 1 TP50 1 TP49 1 J35 2 1 R66 1 J34 2 1 R65 IC2NEG IC2POS IC1NEG IC1POS IC5NEG IC5POS 51 1 51 1 51 1 51 1 51 1 51 1 51 1 51 1 IC6NEG IC6POS PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 ...

Page 24: ...23 4 2 1 U14 4 2 1 U13 2 1 R45 1 J22 4 2 1 U12 4 2 1 U11 2 1 R43 1 J21 2 1 R41 4 2 1 U10 4 2 1 U9 1 J20 OC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC5B MFSYNC FSYNC OC3B OC2B OC1B OC5 OC4 OC3 OC2 OC4B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B NC7SZ32 A C B...

Page 25: ...013007 DS3104DK01B0 JML 1 J40 1 J41 1 J38 1 J39 1 TP59 1 TP60 1 TP57 1 TP58 1 TP4 1 TP3 1 TP2 1 TP1 1 J15 1 J5 1 J4 1 J2 OC4POS OC4NEG OC5POS OC5NEG OC6NEG OC6POS OC7NEG OC7POS PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 ...

Page 26: ...INTENTIONALLY LEFT BLANK 7 OF 12 Wed Feb 21 13 57 17 2007 JML DS3104DK01B0 013007 PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 ...

Page 27: ...5 36 37 U42 SCLK 0 0 POR 0 0 0 0 RX232 CS USB_RXD USB_TXD 10UF SDI RXD0 11 0592MHZ RX232 TX232 TX232 TXD0 RXD0 RS232 10UF 10UF 10UF 10UF TXD0 INTREQ 22PF 22PF 10K NA 330 GREEN PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 VCC NC7SZ32 A C B CONN_DB9P H G F C A B D E J DS87C520_TQFP P1_5 GND 2 0 XTAL2 VCC AD0 AD1 AD2 AD4 AD6 AD7 ALE PSEN P2_7 P2_6 P2_5 P2_3 P2_4 P2_2 P2_1 ...

Page 28: ...16 15 14 13 22 21 10 3 28 27 1 23 U46 USBPWR NA 1UF 10K 10K NA 10K 10K 0 0 0 0 USB_RXD USB_TXD 10K 4 38V JTCLK 10K 10K JTMS JTDI JTRST JTDO 0 0 0 0 3 08V POR PORNOT 1UF 4 7UF PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 MAX811_U RESET VCC GND MR VCC MAX812_U VCC GND MR RESET V5_0 CP2101_U1 USBDM VBUS USBDP RTS DTR CTS DSR DCD RI NC7 NC8 NC9 NC10 NC11 RST REGIN NC6 NC4 N...

Page 29: ...2 1 C14 7 11 6 15 14 13 12 5 4 3 2 10 U6 1 AMP 2 1MM 5 5MM USBPWR V5_0 330 NA DUT18 68UF OSC33 DUT33 VDDIOB DUT18 DUT33 4 7UF 6 8UF 6 8UF 4 7UF 6 8UF 6 8UF 330 330 330 OSC33 4 7UF 1 AMP 4 7UF DUT33 PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 V5_0 MAX1793 IN2 IN1 IN3 OUT3 OUT2 OUT4 OUT1 RST SET IN4 SHDN GND NC7SZ32 A C B MAX1793_U2 IN2 IN3 GND SHDN IN4 IN1 SET RST OUT1 ...

Page 30: ...2 1 C79 2 1 C83 2 1 C87 2 1 C91 2 1 C95 2 1 C99 2 1 C103 2 1 C108 2 1 C112 2 1 C116 1 TP75 1 TP76 1 TP77 1 TP78 2 1 C120 2 1 C124 2 1 C128 2 1 C132 1 TP79 1 TP81 1 TP80 2 1 C107 2 1 C111 2 1 C115 2 1 C119 2 1 C123 2 1 C127 2 1 C131 2 1 C136 1 TP82 2 1 C135 2 1 C153 2 1 C154 2 1 C155 2 1 C169 2 1 C168 2 1 C139 2 1 C141 2 1 C143 2 1 C145 2 1 C147 2 1 C151 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF ...

Page 31: ...F TO 100 UF REVISION HISTORY A0 051707 GENERAL CLEANUP RELEASE TO DATASHEET ON DS OSC OTHER CHANGES MADE PER DESIGN REVIEW B0 052907 FIXED USBPWR NET FIXED SILKSCREEN BELOW SONSDH HEADER Tue May 29 13 45 02 2007 JML 12 OF 12 013007 DS3104DK01B0 PAGE DATE TITLE ENGINEER A A B B C C D D 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 ...

Page 32: ...ations and industrial and alternative energy markets Products include high performance high reliability analog and RF devices mixed signal and RF integrated circuits customizable SoCs FPGAs and complete subsystems Microsemi is headquartered in Aliso Viejo Calif Learn more at www microsemi com 2012 Microsemi Corporation All rights reserved Microsemi and the Microsemi logo are trademarks of Microsem...

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