PIC24FV16KM204 FAMILY
DS33030A-page 118
Advance Information
2013 Microchip Technology Inc.
REGISTER 8-35:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0
U-0
R/W-0
U-0
R-0
R-0
R-0
R-0
CPUIRQ
—
VHOLD
—
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
U-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
—
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CPUIRQ:
Interrupt Request from Interrupt Controller CPU bit
1
= An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will
happen when the CPU priority is higher than the interrupt priority)
0
= No interrupt request is left unacknowledged
bit 14
Unimplemented:
Read as ‘
0
’
bit 13
VHOLD:
Vector Hold bit
Allows Vector Number Capture and Changes which Interrupt is Stored in the VECNUM<6:0> bits:
1
= VECNUM<6:0> will contain the value of the highest priority pending interrupt, instead of the
current interrupt
0
= VECNUM<6:0> will contain the value of the last Acknowledged interrupt (last interrupt that has
occurred with higher priority than the CPU, even if other interrupts are pending)
bit 12
Unimplemented:
Read as ‘
0
’
bit 11-8
ILR<3:0>:
New CPU Interrupt Priority Level bits
1111
= CPU Interrupt Priority Level is 15
•
•
•
0001
= CPU Interrupt Priority Level is 1
0000
= CPU Interrupt Priority Level is 0
bit 7
Unimplemented:
Read as ‘
0
’
bit 6-0
VECNUM<6:0>:
Vector Number of Pending Interrupt bits
0111111
= Interrupt vector pending is Number 135
•
•
•
0000001
= Interrupt vector pending is Number 9
0000000
= Interrupt vector pending is Number 8
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