Advanced Chipset Features Option
This option displays a table of items that define critical timing
parameters of the mainboard. You should leave the items on
this page at their default values unless you are very familiar
with the technical specifications of your system hardware. If
you change the values incorrectly, you may introduce fatal er-
rors or recurring instability into your system.
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
Advanced Chipset Features
Item Help
Bank 0/1 DRAM Timing
SDRAM 8/10ns
Bank 2/3 DRAM Timing
SDRAM 8/10ns
Bank 4/5 DRAM Timing
SDRAM 8/10ns
SDRAM Cycle Length
3
DRAM Clock
Host CLK
Memory
Hole
Disabled
P2C/C2P
Concurrency
Enabled
Fast R-W Turn Around
Disabled
System BIOS Cacheable
Enabled
Video RAM Cacheable
Enabled
AGP Aperture Size
64M
AGP-4X
Mode
Enabled
AGP Driving Control
Auto
x AGP Driving Value
DA
AGP Fast Write
Disabled
OnChip
USB
Enabled
USB Keyboard Support
Disabled
OnChip
Sound
Auto
Menu Level
↑
↓
→
←
: Move
Enter : Select
+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous
Values
F6:Fail-Safe
Defaults F7:Optimized
Defaults
Bank 0/1 2/3 4/5 DRAM Timing (8/10 ns)
The DRAM timing is controlled by the DRAM Timing Regis-
ters. The timings programmed into this register are dependent
on the system design. Slower rates may be required in certain
system designs to support loose layouts or slower memory.
SDRAM Cycle Length (3)
This item sets the timing and wait states for SDRAM memory.
We recommend that you leave this item at the default value.
DRAM Clock (Host CLK)
This item sets the DRAM Clock. We recommend that you
leave this item at the default value.
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