December 20, 2005
10
be used to provide single ended LVTTL clock input to the FPGA via an 8 or 4-pin oscillator. The
following figure shows the clock resources on the Virtex-4 MB development board.
Virtex-4™
XC4VL25/LX60-FF668
Programmable
LVDS Clock
Source
Bank 1
Bank 3
Bank 4
C15
B13
A16
B15
AE14
AE10
D12
E13
AF11
AF10
SAM
CLock
OSC
Socket
ETH_TXC
ETH_RXC
CLK_SOCKET
CLK_PROG_N
CLK_PROG_P
SPI_RDCLK_N
SPI_RDCLK_P
LVTTL
OSC
@100
MHz
SMA
Connectors
LIO_CLKIN_N
LIO_CLKIN_P
P240
Differential
CLock
SPI_TSCLK
LIO_CLKIN_0
LIO_CLKIN_1
P240
Single-ended
CLock
SPI
Status
Clock
CLK_100
DDR_CLK
DDR
Feedback
Clock
B17
A17
A10
B10
SAM_CLK
Bank 10
R8
Figure 6 - Clock Sources on the Virtex-4 MB Board