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Memec Virtex-4 User Manual Download Page 19

 

 

December 20, 2005 

16 

Virtex-4

FPGA

ICS8442

CLKOUT0

CLKOUT1

SMA

Connectors

CONTROL

CLK_PROG_P

CLK_PROG_N

SW3

SW9

M[8:0]

N1:0]

25Mhz

 

Figure 9 – ICS8442 Clock Synthesizer M and N DIP Switches 

 
The following tables show the DIP Switch settings for M and N selections. Please refer to Table 6 
for the information on pull-up and pull-down resistors provided internal to the ICS8442 device for 
the M and N input signals. 

 

Synthesizer

5

4

3

2

1

6

7

8

M8

10

9

ON

2

1

ON

M7

M6

M5

M4

M3

M2

M1

M0

N1

N0

3.3V

OFF

OFF

SW9

SW3

 

 

Figure 10 – M and N DIP Switches for the Synthesizers

 

 
 
 
 
 
 
 

Summary of Contents for Virtex-4

Page 1: ...Virtex 4 MB Development Board User s Guide Version 3 0 December 2005 ...

Page 2: ...ICS8442 Clock Generation 13 3 4 4 ICS8442 Programming Modes 14 3 4 5 ICS8442 M and N Settings 14 3 5 10 100 ETHERNET PHY 18 3 6 LCD PANEL 20 3 7 USB 2 0 TO RS232 PORT 20 3 8 RS232 21 3 9 USER DIP AND PB SWITCHES 22 3 10 USER LEDS 23 3 11 VBAT JUMPER 23 3 12 CONFIGURATION AND DEBUG PORTS 23 3 12 1 JTAG Chain 23 3 12 2 System ACE Module Connector 24 3 12 3 Serial Data Flash 26 3 12 4 JTAG Port PC4 3...

Page 3: ...CE TO THE FPGA 15 FIGURE 9 ICS8442 CLOCK SYNTHESIZER M AND N DIP SWITCHES 16 FIGURE 10 M AND N DIP SWITCHES FOR THE SYNTHESIZERS 16 FIGURE 11 10 100 ETHERNET INTERFACE 19 FIGURE 12 USB 2 0 TO RS232 SERIAL INTERFACE 21 FIGURE 13 RS232 INTERFACE 22 FIGURE 14 VITEX 4 MB DEVELOPMENT BOARD JTAG CHAIN 24 FIGURE 15 SYSTEMACE MODULE 25 FIGURE 16 VIRTEX 4 MB DEVELOPMENT BOARD CONFIGURATION INTERFACE 26 FIG...

Page 4: ...sor based applications enabling software design teams early access to a hardware platform prior to working with the final product target board The Virtex 4 MB system board utilizes the Xilinx XC4VLX25 LX60 SX35 10FF668C FPGA The board includes 64MB of DDR SDRAM 4MB of Flash 16 bit LVDS Transmit and Receive ports programmable LVDS clock source USB RS232 Bridge a 10 100 Ethernet PHY 100 MHz clock so...

Page 5: ...of Flash 16 Bit LVDS Transmit and Receive Interfaces 10 100 Ethernet PHY Programmable LVDS Clock Source 25 700 MHz User LVDS Clock Outputs via Differential SMA Connectors On board 100MHz LVTTL Oscillator On board LVTTL Oscillator Socket 4 8 Pin Oscillators P240 Connectors LCD Panel 32Mb Serial Flash for FPGA configuration PC4 JTAG Programming Configuration Port SystemACE Module Connector RS232 Por...

Page 6: ... Clock Output 2 5V Regulator 1 2V Regulator Flash 4MB 16 Bit LVDS Transmit Receive 10 100 PHY Figure 1 Virtex 4 MB Development Platform Block Diagram 3 1 LVDS Interface The Virtex 4 MB development board provides high speed LVDS connectors supporting a SPI 4 2 interface This interface consists of 36 LVDS signal pairs 72 FPGA signals and 6 single ended signals In addition to the SPI 4 2 interface th...

Page 7: ...nk Layer Receive Link Layer LVDS Connectors RDat 15 0 RDClk RCtl RStat 1 0 RSClk RDat 15 0 RDClk RCtl RStat 1 0 RSClk SysClk_P LVDS Signals LVTTL Signals LVDS Signals LVTTL Signals SysClk_N Figure 2 SPI 4 2 Interface 3 1 2 SPI 4 2 Pin Assignments The following table shows the SPI 4 2 pin assignments for the 4VLX25 LX60 SX35 FPGA in the FF668 pin package These pin assignments must be used in the bo...

Page 8: ...7 55 56 TDat_P 6 C4 GND 57 58 GND D6 TDat_N 5 59 60 TDat_N 4 E5 E7 TDat_P 5 61 62 TDat_P 4 E6 GND 63 64 GND G7 TDat_N 3 65 66 TDat_N 2 C1 F7 TDat_P 3 67 68 TDat_P 2 C2 GND 69 70 GND H7 TDat_N 1 71 72 TDat_N 0 E4 H8 TDat_P 1 73 74 TDat_P 0 D3 GND 75 76 GND C8 TCtl_N 77 78 TDCLK_N F9 D9 TCtl_P 79 80 TDCLK_P E9 GND 81 82 GND GND 83 84 GND GND 85 86 GND GND 87 88 GND Table 2 SPI 4 2 Receive Pin Assign...

Page 9: ...Dat_P 0 Y10 GND 75 76 GND AA1 RCtl_N 77 78 RDCLK_N AF10 AB1 RCtl_P 79 80 RDCLK_P AF11 GND 81 82 GND GND 83 84 GND GND 85 86 GND GND 87 88 GND 3 1 3 LVDS Connector The design of the SPI 4 2 interface requires use of a high speed and high quality connector The V4MB development board uses the SAMTEC QSE type connector for this interface The QSE 040 01 L Dx A connector from SAMTEC provides up to 28 LV...

Page 10: ...DRAM 64MB Control Data 0 15 Address 0 12 Figure 4 DDR SDRAM Interface Table 3 DDR SDRAM Interface Pin Assignments Signal Name Description FPGA Pin ddr_addr 0 Address 0 N23 ddr_addr 1 Address 1 K23 ddr_addr 2 Address 2 N24 ddr_addr 3 Address 3 J23 ddr_addr 4 Address 4 V23 ddr_addr 5 Address 5 P23 ddr_addr 6 Address 6 U23 ddr_addr 7 Address 7 P24 ddr_addr 8 Address 8 T24 ddr_addr 9 Address 9 R23 ddr...

Page 11: ...trobe1 N19 ddr_csn Chip Select L24 ddr_rasn Row Address Strobe M21 ddr_casn Column Address Strobe M23 ddr_wen Write Enable L21 ddr_clk Clock R20 ddr_clkn Clock R19 ddr_clke Clock Enable K21 3 3 Flash The Virtex 4 MB development board provides 4MB of flash memory x16 A high level block diagram of the flash interface is shown below followed by a table describing the flash memory interface signals Vi...

Page 12: ...L4 flash_d 12 Data 12 M3 flash_d 13 Data 13 N3 flash_d 14 Data 14 P4 flash_d 15 Data 15 R4 flash_cen Chip Select M1 flash_oen Output Enable N2 flash_wen Write Enable J5 flash_rdy Ready M5 flash_reset Reset K5 3 4 Clock Sources The Clock Generation section of the Virtex 4 MB board provides all the necessary clocks for a MicroBlaze processor the I O devices located on the board as well as the DDR SD...

Page 13: ...lock Source Bank 1 Bank 3 Bank 4 C15 B13 A16 B15 AE14 AE10 D12 E13 AF11 AF10 SAM CLock OSC Socket ETH_TXC ETH_RXC CLK_SOCKET CLK_PROG_N CLK_PROG_P SPI_RDCLK_N SPI_RDCLK_P LVTTL OSC 100 MHz SMA Connectors LIO_CLKIN_N LIO_CLKIN_P P240 Differential CLock SPI_TSCLK LIO_CLKIN_0 LIO_CLKIN_1 P240 Single ended CLock SPI Status Clock CLK_100 DDR_CLK DDR Feedback Clock B17 A17 A10 B10 SAM_CLK Bank 10 R8 Fig...

Page 14: ...put is connected to a 100MHz LVTTL oscillator CLK_SOCKET AE14 LVTTL Clock Input LVTTL socket on the Virtex 4 board SPI_TSCLK R8 SPI 4 2 Transmit Status Clock Input This clock input is connected to the SPI 4 2 transmit status clock output ETH_RXC A16 Ethernet Receive Clock Input This clock input is connected to the Ethernet receive clock ETH_TXC B15 Ethernet Transmit Clock Input This clock input is...

Page 15: ... down The N divider inputs latched on the ris ing edge of the nP_LOAD signal TEST Output The TEST output is active during the serial mode of operations Please refer to the datasheet for more information MR Input Pull down Active high reset signal S_CLOCK Input Pull down Serial interface clock input Data is shifted into the device on the rising edge of this clock S_DATA Input Pull down Serial inter...

Page 16: ...k Input FOUT 0 1 0 0 TEST_CLK TEST_CLK N the TEST_CLK must be between 10 and 25MHz This mode can be used to test the ICS8442 device by routing the input clock to the outputs 0 1 25MHz crystal 25MHz crystal N This mode can be used to test the ICS8442 device by routing the 25MHz crystal clock to the outputs 1 0 TEST_CLK ICS8442 PLL Output N Normal Operation 1 1 25MHz crystal ICS8442 PLL Output N Nor...

Page 17: ...1 1 0 Infiniband 125 0 0 0 0 1 0 1 0 0 1 0 XAUI 156 25 0 0 0 0 1 1 0 0 1 1 0 3 4 4 ICS8442 Programming Modes The ICS8442 provides two different methods of programming the M and N values into the device a Parallel Mode and a Serial Mode In parallel mode M and N values are programmed into the device when the nP_LOAD signal pulses low In the serial mode the I2C pins S_DATA and S_CLOCK along with the ...

Page 18: ...ck Synthesizer Interface to the FPGA As shown in the above figure the ICS8442 device outputs two identical LVDS clock sources One of these clock sources can be used to provide the reference clock input to the LVDS interface on the Virtex 4 MB development board while the other clock output can be used to trigger a scope during testing The second output could also be used to provide a low jitter LVD...

Page 19: ...witches The following tables show the DIP Switch settings for M and N selections Please refer to Table 6 for the information on pull up and pull down resistors provided internal to the ICS8442 device for the M and N input signals Synthesizer 5 4 3 2 1 6 7 8 M8 10 9 ON 2 1 ON M7 M6 M5 M4 M3 M2 M1 M0 N1 N0 3 3V OFF OFF SW9 SW3 Figure 10 M and N DIP Switches for the Synthesizers ...

Page 20: ... 0 MHz M 8 0 N 1 0 FOUT 1 0 MHz 000001000 11 25 Min 000011000 10 150 000001001 11 28 125 000011001 10 156 25 000001010 11 31 25 000001101 01 162 5 000001011 11 34 375 000011010 10 162 5 000001100 11 37 5 000011011 10 168 75 000001101 11 40 625 000001110 01 175 000001110 11 43 75 000011100 10 175 000001111 11 46 875 000001111 01 187 5 000001000 10 50 000001000 00 200 000010000 11 50 000010000 01 20...

Page 21: ...esizer using the parallel mode configuration along with the DIP switch settings for M and N SYNTH_RESET K1 This input signal resets the synthesizer SYNTH_SCLK L1 This clock input is used to load the M and N values into the synthesizer using serial mode configuration SYNTH_SDATA T4 Serial data input to the synthesizer for loading the M and N values SYNTH_SLOAD T3 This input signal is used to load t...

Page 22: ...TH_RESETn ETH_MDIO Figure 11 10 100 Ethernet Interface The following table shows the FPGA pin assignments for the Ethernet interface Table 14 Ethernet Pin Assignments Signal Name Virtex 4 Pin ETH_TXC B15 ETH_RXC A16 ETH_CRS B14 ETH_RXDV H1 ETH_RXD 0 G4 ETH_RXD 1 G3 ETH_RXD 2 F3 ETH_RXD 3 H4 ETH_COL C14 ETH_RXER H2 ETH_TXEN G2 ETH_TXER G1 ETH_TXD 0 H5 ETH_TXD 1 H6 ETH_TXD 2 F1 ETH_TXD 3 C12 ETH_MDC...

Page 23: ...g from 300 to 921 600 baud The CP2102 is a highly integrated USB to UART Bridge Controller providing a simple solution for USB serial communications using a minimum of components and PCB space The CP2102 includes a USB 2 0 full speed function controller USB transceiver oscillator EEPROM and asynchronous serial data bus UART with full modem control signals in a compact 5mm X 5mm MLP 28 package No o...

Page 24: ...T L6 RS232 transmit signal USB 2 0 Signals D NA USB D signal D NA USB D signal Common Signal USB_RESETn R6 CP2102 reset signal To use the USB port the CP2102 device drivers must be installed These drivers are included on the Virtex 4 MB Development Kit CD and contained in the self extracting file CP2101 exe To install the CP2101 2 virtual COM port device drivers refer to Appendix A 3 8 RS232 The V...

Page 25: ...ll a jumper on pins 1 2 Install a jumper on pins 2 3 A Jumper must be installed on JP22 if RTS and CTS signal connections are needed 3 9 User DIP and PB Switches The Virtex 4 MB development board provides four user push button switches as described in the following table An active low signal is generated when a given switch is pressed Table 19 Push Button Switch Pin Assignments Signal Name Descrip...

Page 26: ...s used to provide user access to the VBAT input of the FPGA If user is not sourcing the VBAT voltage a jumper must be installed on pins 1 2 of the JP27 jumper User can source voltage to the VBAT input via pins 2 and 3 of this jumper The following table shows the pin assignments for the VBAT jumper Table 22 VBAT Jumper JP27 Pin Number Description 1 2 5V 2 VBAT 3 Ground 3 12 Configuration and Debug ...

Page 27: ...Module SAM The SAM can be used to configure the FPGA or to provide bulk flash memory to the MicroBlaze processor The Virtex 4 MB development board provides a System ACE interface that can be used to configure the Virtex 4 FPGA The interface also gives software designers the ability to run real time operating systems RTOS from removable CompactFlash cards The Memec System ACE module DS KIT SYSTEMAC...

Page 28: ...2 2 1 System ACE Controller Signal Description The following table shows the System ACE Module signal assignments to the FPGA I O pins Table 23 SAM Interface Signals Virtex 4 Pin System ACE Signal Name SAM Connector Pin JP16 System ACE Signal Name Virtex 4 Pin 3 3V 1 2 3 3V TDO 3 4 GND TMS 5 6 CLOCK AE10 TDI 7 8 GND PROGRAMn 9 10 TCK GND 11 12 GND AB7 OEn 13 14 INITn AB6 MPA0 15 16 WEn V6 Y5 MPA2 ...

Page 29: ...n the Memec Virtex 4 MB development board This serial flash along with a CPLD is used to configure the Virtex 4 FPGA located on the development board on power up The following figure shows a high level block diagram of the serial flash interface to the Virtex 4 FPGA Virtex 4 FPGA XC9536XV CPLD CCLK DIN INITn DONE Atmel AT45DB321B Serial Flash SI SO SCK CSn Master Serial Interface SPI Interface FPG...

Page 30: ...rite protect input signal U25 FPGA_RESETn Serial Flash SPI port reset input signal M25 FPGA_RDY BUSYn Serial Flash SPI port ready output signal V26 The primary function of the CPLD is to translate the Master Serial interface to the SPI interface of the serial flash The XC9536XV CPLD uses the FPGA CCLK clock along with the INITn and DONE signals to drive the SPI SI SCK and CSn signals The SO output...

Page 31: ...mpers installed on pins 1 2 and 4 5 FPGA only in the JTAG chain Table 25 JTAG Chain Jumper Settings Devices in the JTAG Chain JP18 Jumpers Installed CPLD and FPGA Pins 1 2 3 4 and 5 6 CPLD Pins 2 3 and 5 6 FPGA Pins 1 2 and 4 5 3 12 3 2 Configuration Flash on the Virtex 4 MB Development Board The following figure shows the detail interface between the FPGA and the serial flash A PC4 cable is used ...

Page 32: ...zip it After unzipping this file a folder called C Flash_Utilities is created 2 In order to program the flash flash programming utilities included in the xapp800 must be downloaded from the following web site http www xilinx com products xaw coolvhdlq htm 3 Click on the above link to download the xapp800 zip file and unzip it to a temporary folder on your hard drive You need to register prior to d...

Page 33: ...hen generating the MCS file in iMPACT for the Virtex 4 MB board Table 27 Platform Flash Selection FPGA Platform Flash Used LX25 XCF08P XCF16P or XCF32P LX60 XCF32P Sx35 XCF16P or XCF32P 7 Un install JP9 jumpers 8 Make sure JP12 jumper is un installed When JP12 jumper is un installed the CPLD outputs are placed in the tri state mode allowing the Flash Programming Header to drive the serial flash SP...

Page 34: ...back to the step 11 and re program the flash 13 Upon completion of the serial flash programming power down the board and remove the PC4 cable from the Flash Programming header 14 Set the mode jumpers to Master Serial install all mode jumpers on JP9 15 Install a jumper on JP12 16 Power up the board and FPGA will configure 3 12 4 JTAG Port PC4 The Virtex 4 MB development board provides a JTAG port P...

Page 35: ...ators The following figure shows the voltage regulators that are used on Virtex 4 MB development board to provide various on board voltage sources As shown in the following figure a connector is used to provide the main 5 0V voltage to the board This voltage source is provided to all on board regulators to generate the 1 2V 2 5V and 3 3V voltages 3 3V Regulator 2 5V Regulator 1 2V Regulator 5 0V C...

Page 36: ... O Bank Voltages Bank I O Voltage 0 2 5V 1 2 5V 3 3V 2 2 5V 3 3V 3 2 5V 4 2 5V 5 2 5V 3 3V 6 2 5V 7 2 5V 3 3V 8 2 5V 9 2 5V 10 3 3V 3 15 P240 Expansion Module Signal Assignments The following tables show the Virtex 4 pin assignments to the P240 Expansion Module connectors JX1 JX2 located on the Virtex 4 MB development board Table 31 P240 Connector Pin Assignments Virtex 4 FPGA Pin I O Connector Si...

Page 37: ...O_LVDS_P14 71 72 LIO_LVDS_P15 C21 H21 LIO_LVDS_N14 73 74 LIO_LVDS_N15 B21 GND 75 76 GND F20 LIO_LVDS_P12 77 78 LIO_LVDS_P13 F18 E20 LIO_LVDS_N12 79 80 LIO_LVDS_N13 E18 G19 LIO_LVDS_P10 81 82 LIO_LVDS_P11 E21 F19 LIO_LVDS_N10 83 84 LIO_LVDS_N11 D21 GND 85 86 GND H20 LIO_LVDS_P8 87 88 LIO_LVDS_P9 D20 G20 LIO_LVDS_N8 89 90 LIO_LVDS_N9 D19 GND 91 92 GND D22 LIO_LVDS_P6 93 94 LIO_LVDS_P7 E17 C22 LIO_LV...

Page 38: ...34 RIO_SE_27 AB21 V20 RIO_SE_24 35 36 RIO_SE_25 W22 AD26 RIO_SE_22 37 38 RIO_SE_23 Y22 W20 RIO_SE_20 39 40 RIO_SE_21 W21 AD25 RIO_SE_18 41 42 RIO_SE_19 AC21 AD19 RIO_SE_16 43 44 RIO_SE_17 AC19 2 5V 45 46 2 5V 2 5V 47 48 2 5V 2 5V 49 50 2 5V 2 5V 51 52 2 5V AA16 RIO_SE_14 53 54 RIO_SE_15 AC16 AA15 RIO_SE_12 55 56 RIO_SE_13 AC15 AB14 RIO_SE_10 57 58 RIO_SE_11 AC14 AA14 RIO_SE_8 59 60 RIO_SE_9 AD14 A...

Page 39: ...02 RIO_LVDS_N5 AD21 GND 103 104 GND AF19 RIO_LVDS_P2 105 106 RIO_LVDS_P3 AC18 AF20 RIO_LVDS_N2 107 108 RIO_LVDS_N3 AB18 GND 109 110 GND AF18 RIO_LVDS_P0 111 112 RIO_LVDS_P1 Y19 AE18 RIO_LVDS_N0 113 114 RIO_LVDS_N1 W19 GND 115 116 GND Y17 RIO_CLKOUT_P 117 118 RIO_CLKOUT_1 U7 AA17 RIO_CLKOUT_N 119 120 RIO_CLKOUT_0 U6 GND 121 122 GND GND 123 124 GND GND 125 126 GND GND 127 128 GND GND 129 130 GND GND...

Page 40: ...December 20 2005 37 Appendix A 1 Double click CP2101_Drivers exe Launching CP2101 Driver Installation 2 Click Next 3 Read the license agreement and then click Yes Cygnal License Agreement ...

Page 41: ...ory and then click Next CP2101 Destination Location 5 The drivers are extracted to the selected directory Click Finish once the extraction completes CP2101 Installation Successful 6 To finish the installation plug the USB cable into the board and a USB port on the PC ...

Page 42: ...ck the radio button to Install the software automatically Recommended and then click Next Found New Hardware Wizard 9 The driver installation begins If installing on WindowsXP a warning is received stating that Windows Logo testing has not passed as shown below Click Continue Anyway Windows Logo Testing Not Passed ...

Page 43: ...to UART Bridge Controller CP2101 Recognized as COM Port 13 If the CP2101 does not show up under ports it may show up under Other Devices with a yellow exclamation mark In this case unplug the USB cable run the setup manually C Cygnal CP2101 WIN Setup exe and then plug the USB cable back in 14 The O S automatically assigns a COM Port number typically between COM3 and COM7 For consistency the COM nu...

Page 44: ...December 20 2005 41 COM Port Properties 15 Change to the Port Settings tab and select Advanced Port Settings Advanced 16 Select COM10 in the COM Port Number field and then click OK twice ...

Page 45: ...er 20 2005 42 Changing the COM Port Number 17 Close the Device Manager and then re open it Under Ports the CP2101 USB to UART Bridge Controller is now assigned to COM10 as shown below CP2101 Assigned to COM10 ...

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